In high-current applications where several FETs are connected in parallel, the gate slew rate control for the main FETs is not recommended due to unequal distribution of inrush currents among the FETs. This action makes FET selection complex and results in over sizing of the FETs.

The TPS48111-Q1 integrates precharge gate driver (G) with a dedicated control input (INP_G). This feature can be used to drive a separate FET that can be used to precharge the capacitive load. Figure 8-7 shows the precharge FET implementation for capacitive load charging using TPS48111-Q1. An external capacitor Cg reduces the gate turn-ON slew rate and controls the inrush current.

Figure 8-7 Capacitor Charging Using Gate Slew Rate Control of Precharge FET

During power up with EN/UVLO high and C_BST voltage above V_{(BST_UVLOR)} threshold, INP and INP_G controls are active. For the precharge functionality, drive INP low to keep the main FETs OFF and drive INP_G high. G output gets pulled up to BST with I_G. Use Equation 5 to calculate the required C_g value.

Where,

I_(G) is 100 µA (typical) and C_LOAD is total load capacitance.

Use Equation 6 to calculate the I_INRUSH. A series resistor R_g must be used in conjunction with C_g to limit the discharge current from C_g during turn-off . The recommended value for R_g is between 220 Ω to 470 Ω. After the output capacitor is charged, turn OFF the precharge FET by driving INP_G low. G gets pulled low to SRC with an internal 135-mA pulldown switch. The main FETs can be turned ON by driving INP high.

Figure 8-8 shows other system design approaches to charge large output capacitors in high current applications. The designs involve an additional power resistor in series in series with precharge FET. The back-to-back FET topology shown is typically used in bi-directional power control applications like battery management systems.