ZHCSB50K December 2012 – May 2019 TPS50301-HT
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 说明 （续）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 VIN and Power VIN Pins (VIN and PVIN)
- 8.3.2 PVIN vs Frequency
- 8.3.3 Voltage Reference
- 8.3.4 Adjusting the Output Voltage
- 8.3.5 Maximum Duty Cycle Limit
- 8.3.6 PVIN vs Frequency
- 8.3.7 Safe Start-Up into Prebiased Outputs
- 8.3.8 Error Amplifier
- 8.3.9 Slope Compensation
- 8.3.10 Enable and Adjust UVLO
- 8.3.11 Adjustable Switching Frequency and Synchronization (SYNC)
- 8.3.12 Slow Start (SS/TR)
- 8.3.13 Power Good (PWRGD)
- 8.3.14 Bootstrap Voltage (BOOT) and Low Dropout Operation
- 8.3.15 Sequencing (SS/TR)
- 8.3.16 Output Overvoltage Protection (OVP)
- 8.3.17 Overcurrent Protection
- 8.3.18 TPS50301-HT Thermal Shutdown
- 8.3.19 Turn-On Behavior
- 8.3.20 Small Signal Model for Loop Response
- 8.3.21 Simple Small Signal Model for Peak Current Mode Control
- 8.3.22 Small Signal Model for Frequency Compensation
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Custom Design With WEBENCH® Tools
- 9.2.2.2 Operating Frequency
- 9.2.2.3 Output Inductor Selection
- 9.2.2.4 Output Capacitor Selection
- 9.2.2.5 Input Capacitor Selection
- 9.2.2.6 Slow Start Capacitor Selection
- 9.2.2.7 Bootstrap Capacitor Selection
- 9.2.2.8 Undervoltage Lockout (UVLO) Set Point
- 9.2.2.9 Output Voltage Feedback Resistor Selection
- 9.2.2.10 Compensation Component Selection
- 9.2.3 Parallel Operation
- 9.2.4 Application Curve
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
8.3.15 Sequencing (SS/TR)
Many of the common power-supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins.
The sequential method is shown in Figure 22 using two TPS50301-HT devices. The power good of the first device is coupled to the EN pin of the second device, which enables the second power supply after the primary supply reaches regulation.
Figure 23 shows the method implementing ratiometric sequencing by connecting the SS/TR pins of two devices together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow-start time, the pullup current source must be doubled in Equation 7.
Ratiometric and simultaneous power-supply sequencing can be implemented by connecting the resistor network of R1 and R2 (shown in Figure 24) to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 9 and Equation 10, the tracking resistors can be calculated to initiate the Vout2 slightly before, after, or at the same time as Vout1. Equation 11 is the voltage difference between Vout1 and Vout2.
To design a ratiometric start-up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 9 and Equation 10 for ΔV. Equation 11 results in a positive number for applications where the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.
The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset, 29 mV) in the slow-start circuit and the offset created by the pullup current source (Iss, 2 μA) and tracking resistors, the Vssoffset and Iss are included as variables in the equations.
To ensure proper operation of the device, the calculated R1 value from Equation 9 must be greater than the value calculated in Equation 12.
Figure 24. Ratiometric and Simultaneous Start-Up Sequence