8.3.21 Simple Small Signal Model for Peak Current Mode Control

Figure 26 is a simple small signal model that can be used to understand how to design the frequency compensation. The device power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. Equation 13 shows the control to output transfer function, which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 25) is the power stage transconductance (gm_ps), which is 18 A/V for the device. The dc gain of the power stage is the product of gm_ps and the load resistance (R_L) as shown in Equation 14 with resistive loads. As the load current increases, the dc gain decreases. This variation with load may seem problematic at first glance, but fortunately, the dominant pole moves with load current (see Equation 15). The combined effect is highlighted by the dashed line in Figure 27. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions, which makes it easier to design the frequency compensation.

Figure 26. Simplified Small Signal Model for Peak Current Mode Control

Figure 27. Simplified Frequency Response for Peak Current Mode Control

Equation 13.

Equation 14.

Equation 15.

Equation 16.

where

• gm_ea is the GM amplifier gain (1300 μA/V).
• gm_ps is the power stage gain (18 A/V).
• R_L is the load resistance.
• C_O is the output capacitance.
• R_ESR is the equivalent series resistance of the output capacitor.