ZHCSB50K December 2012 – May 2019 TPS50301-HT
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 说明 （续）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 VIN and Power VIN Pins (VIN and PVIN)
- 8.3.2 PVIN vs Frequency
- 8.3.3 Voltage Reference
- 8.3.4 Adjusting the Output Voltage
- 8.3.5 Maximum Duty Cycle Limit
- 8.3.6 PVIN vs Frequency
- 8.3.7 Safe Start-Up into Prebiased Outputs
- 8.3.8 Error Amplifier
- 8.3.9 Slope Compensation
- 8.3.10 Enable and Adjust UVLO
- 8.3.11 Adjustable Switching Frequency and Synchronization (SYNC)
- 8.3.12 Slow Start (SS/TR)
- 8.3.13 Power Good (PWRGD)
- 8.3.14 Bootstrap Voltage (BOOT) and Low Dropout Operation
- 8.3.15 Sequencing (SS/TR)
- 8.3.16 Output Overvoltage Protection (OVP)
- 8.3.17 Overcurrent Protection
- 8.3.18 TPS50301-HT Thermal Shutdown
- 8.3.19 Turn-On Behavior
- 8.3.20 Small Signal Model for Loop Response
- 8.3.21 Simple Small Signal Model for Peak Current Mode Control
- 8.3.22 Small Signal Model for Frequency Compensation
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Custom Design With WEBENCH® Tools
- 9.2.2.2 Operating Frequency
- 9.2.2.3 Output Inductor Selection
- 9.2.2.4 Output Capacitor Selection
- 9.2.2.5 Input Capacitor Selection
- 9.2.2.6 Slow Start Capacitor Selection
- 9.2.2.7 Bootstrap Capacitor Selection
- 9.2.2.8 Undervoltage Lockout (UVLO) Set Point
- 9.2.2.9 Output Voltage Feedback Resistor Selection
- 9.2.2.10 Compensation Component Selection
- 9.2.3 Parallel Operation
- 9.2.4 Application Curve
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
9.2.2.10 Compensation Component Selection
There are several industry techniques used to compensate DC-DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60° and 90°. The method presented here ignores the effects of the slope compensation that is internal to the TPS50301-HT. Since the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. Use WEBENCH, Pspice model for simulation.
First, the modulator pole, fpmod, and the esr zero, fzmod must be calculated using Equation 33 and Equation 34. For Cout, use a derated value of 22.4 µF. use Equation 35 and Equation 36 to estimate a starting point for the closed loop crossover frequency fco. Then the required compensation components may be derived. For this design example, fpmod is 12.9 kHz and fzmod is 2730 kHz. Equation 35 is the geometric mean of the modulator pole and the esr zero and Equation 36 is the geometric mean of the modulator pole and one half the switching frequency. Use a frequency near the lower of these two values as the intended crossover frequency fco. In this case Equation 35 yields 175 kHz and Equation 36 yields 55.7 kHz. The lower value is 55.7 kHz. A slightly higher frequency of 60.5 kHz is chosen as the intended crossover frequency.
Now the compensation components can be calculated. First calculate the value for R2 which sets the gain of the compensated network at the crossover frequency. Use Equation 37 to determine the value of R2.
Next calculate the value of C3. Together with R2, C3 places a compensation zero at the modulator pole frequency. Equation 38 to determine the value of C3.
Using Equation 37 and Equation 38 the standard values for R2 and C3 are 1.69 kΩ and 8200 pF.
An additional high frequency pole can be used if necessary by adding a capacitor in parallel with the series combination of R2 and C3. The pole frequency is given by Equation 39. This pole is not used in this design.
