ZHCSEM8 January   2016 TPS50601-SP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  PVIN vs Frequency
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Adjusting the Output Voltage
      5. 8.3.5  Maximum Duty Cycle Limit
      6. 8.3.6  PVIN vs Frequency
      7. 8.3.7  Safe Start-Up into Prebiased Outputs
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Enable and Adjust UVLO
      11. 8.3.11 Adjustable Switching Frequency and Synchronization (SYNC)
      12. 8.3.12 Slow Start (SS/TR)
      13. 8.3.13 Power Good (PWRGD)
      14. 8.3.14 Bootstrap Voltage (BOOT) and Low Dropout Operation
      15. 8.3.15 Sequencing (SS/TR)
      16. 8.3.16 Output Overvoltage Protection (OVP)
      17. 8.3.17 Overcurrent Protection
        1. 8.3.17.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.17.2 Low-Side MOSFET Overcurrent Protection
      18. 8.3.18 TPS50601-SP Thermal Shutdown
      19. 8.3.19 Turn-On Behavior
      20. 8.3.20 Small Signal Model for Loop Response
      21. 8.3.21 Simple Small Signal Model for Peak Current Mode Control
      22. 8.3.22 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
      2. 8.4.2 Continuous Current Mode (CCM) Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Slow Start Capacitor Selection
        6. 9.2.2.6 Bootstrap Capacitor Selection
        7. 9.2.2.7 Undervoltage Lockout (UVLO) Set Point
        8. 9.2.2.8 Output Voltage Feedback Resistor Selection
          1. 9.2.2.8.1 Minimum Output Voltage
        9. 9.2.2.9 Compensation Component Selection
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息
    1. 13.1 器件命名规则

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

HKH Package
20-Pin CFP
Bottom View
TPS50601-SP po2_hkh_lvsa94.gif

Pin Functions

PIN DESCRIPTION
NO. NAME
1 GND Return for control circuitry/thermal pad(1)
2 EN EN pin has an internal pullup thus EN pin can be floated to enable the device. As an option external pullup can also be added if desired. Adjust the input undervoltage lockout (UVLO) with two resistors.
3 RT In internal oscillation mode, a resistor is connected between the RT pin and GND to set the switching frequency.
4 SYNC Optional 1-MHz external system clock input. The device operates with an internal oscillator if this pin is left open.
5 VIN Supplies the power to the output FET controllers
6 PVIN Power input. Supplies the power switches of the power converter
7
8 PGND Return for low-side power MOSFET
9
10
11 PH Switch node
12
13
14
15
16 BOOT A bootstrap capacitor is required between BOOT and PH. The voltage on this capacitor carries the gate drive voltage for the high-side MOSFET.
17 VSENSE Inverting input of the gm error amplifier
18 COMP Error amplifier output and input to the output switch current comparator. Connect frequency compensation to this pin.
19 SS/TR Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.
20 PWRGD Power Good fault pin is an open-drain connection. Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or EN shutdown, or during slow start.
(1) Thermal pad (analog ground) must be connected to PGND external to the package.

Bare Die Information

DIE THICKNESS BACKSIDE FINISH BACKSIDE POTENTIAL BOND PAD METALLIZATION COMPOSITION BOND PAD THICKNESS
15 mils. Silicon with backgrind Ground Al5TiN 557.5 nm
TPS50601-SP die_slvsa94.png

Bond Pad Coordinates in Microns

DESCRIPTION PAD NUMBER X MIN Y MIN X MAX Y MAX
GND 1 400.77 5039.325 578.07 5216.625
EN 2 44.19 4169.79 221.49 4347.09
RT 3 44.19 3894.21 221.49 4071.51
SYNC 4 44.19 3618.63 221.49 3795.93
VIN 5 47.565 2952.27 224.865 3129.57
PVIN 6 280.215 2414.115 457.515 2591.415
PVIN 7 280.215 2170.665 457.515 2347.965
PVIN 8 280.215 1928.115 457.515 2105.415
PVIN 9 280.215 1684.665 457.515 1861.965
PGND 10 254.52 1236.285 431.82 1413.585
PGND 11 254.52 1008.315 431.82 1185.615
PGND 12 254.52 780.345 431.82 957.645
PGND 13 254.52 552.375 431.82 729.675
PGND 14 254.52 324.405 431.82 501.705
PGND 15 254.52 96.435 431.82 273.735
PH 16 1590.12 99.405 1767.42 276.705
PH 17 1590.12 321.435 1767.42 498.735
PH 18 1590.12 555.345 1767.42 732.645
PH 19 1590.12 777.375 1767.42 954.675
PH 20 1590.12 1011.285 1767.42 1188.585
PH 21 1590.12 1233.315 1767.42 1410.615
PH 22 1564.335 1684.665 1741.635 1861.965
PH 23 1564.335 1928.115 1741.635 2105.415
PH 24 1564.335 2170.665 1741.635 2347.965
PH 25 1564.335 2414.115 1741.635 2591.415
BOOT 26 1801.71 3352.14 1979.01 3529.44
VSENSE 27 1801.71 3644.145 1979.01 3821.445
COMP 28 1801.71 3940.92 1979.01 4118.22
SS/TR 29 1801.71 4216.5 1979.01 4393.8
PWRGD 30 1463.67 5039.325 1640.97 5216.625
GND 31 1251.09 5039.325 1428.39 5216.625
GND 32 1038.51 5039.325 1215.81 5216.625
GND 33 825.93 5039.325 1003.23 5216.625
GND 34 613.35 5039.325 790.65 5216.6
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