7.3.8 Controling Outputs Using the S3 and S5 Pins

In the DDR, DDR2, DDR3, LPDDR3 or DDR4 memory applications, it is important to maintain the VDDQ voltage level higher than VTT (or VTTREF) voltage including both start-up and shutdown. The TPS51116 device provides this management by simply connecting both the S3 and S5 pins to the sleep-mode signals such as SLP_S3 and SLP_S5 in the notebook PC system. All of VDDQ, VTTREF and VTT are turned on at S0 state (S3 = S5 = high). In S3 state (S3 = low, S5 = high), VDDQ and VTTREF voltages are kept on while VTT is turned off and left at high impedance (high-Z) state. The VTT output is floated and does not sink or source current in this state. In S4/S5 states (S3 = S5 = low), all of the three outputs are disabled. Outputs are discharged to ground according to the discharge mode selected by MODE pin (see VDDQ and VTT Discharge Control section). Each state code represents as follow; S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 2)