10.1 Layout Guidelines

Consider the following points before starting the TPS51200-EP device layout design.

• The input bypass capacitor for VLDOIN should be placed as close as possible to the pin with short and wide connections.
• The output capacitor for VO should be placed close to the pin with short and wide connection in order to avoid additional ESR and/or ESL trace inductance.
• Connect VOSNS to the positive node of each VO output capacitor as a separate trace from the high-current power line. This configuration is strongly recommended to avoid additional ESR and/or ESL. If sensing the voltage at the point of the load is required, attach each output capacitor at that point. This layout design minimizes any additional ESR and/or ESL of ground trace between the GND pin and each output capacitor.
• Consider adding low-pass filter at VOSNS if the ESR of any VO output capacitor is larger than 2 mΩ.
• REFIN can be connected separately from VLDOIN. Remember that this sensing potential is the reference voltage of REFOUT. Avoid any noise-generating lines.
• Tie the negative node of each VO output capacitor to the REFOUT capacitor by avoiding common impedance to the high current path of the VO source and sink current.
• The GND and PGND pins should be connected to the thermal land underneath the die pad with multiple vias connecting to the internal system ground planes (for better result, use at least two internal ground planes). Use as many vias as possible to reduce the impedance between PGND or GND and the system ground plane. Also, place bulk capacitors close to the DIMM load point, route the VOSNS to the DIMM load sense point.
• In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly to the thermal pad. The wide traces of the component and the side copper connected to the thermal land pad help to dissipate heat. Connected the numerous vias that are 0.33 mm in diameter from the thermal land to any internal and solder-side ground plane to increase dissipation.
• Consult the TPS51200-EP-EVM User's Guide (SLUU323) for detailed layout recommendations.

10.2 Layout Example

Figure 30. Layout Recommendation

10.3 Thermal Design Considerations

Because the TPS51200-EP is a linear regulator, the VO current flows in both source and sink directions, thereby dissipating power from the device. When the device is sourcing current, the voltage difference shown in Equation 4 calculates the power dissipation.

Equation 4.

In this case, if the VLDOIN pin is connected to an alternative power supply lower than the V_DDQ voltage, overall power loss can be reduced. During the sink phase, the device applies the VO voltage across the internal LDO regulator. Equation 5 calculates the power dissipation, P_{D_SNK}.

Equation 5.

Because the device does not sink and source current at the same time and the I/O current may vary rapidly with time, the actual power dissipation should be the time average of the above dissipations over the thermal relaxation duration of the system. The current used for the internal current control circuitry from the VIN supply and the VLDOIN supply are other sources of power consumption. This power can be estimated as 5 mW or less during normal operating conditions and must be effectively dissipated from the package.

Maximum power dissipation allowed by the package is calculated by Equation 6.

Equation 6.

where

• T_J(max) is 125°C.
• T_A(max) is the maximum ambient temperature in the system.
• θ_JA is the thermal resistance from junction to ambient.

In an application where the device is mounted on PCB, TI strongly recommends using ψ_JT and ψ_JB, as explained in the section pertaining to estimating junction temperature in the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Using the thermal metrics ψ_JT and ψ_JB, as shown in the Thermal Information table, estimate the junction temperature with corresponding formulas shown in Equation 7. The older θ_JC top parameter specification is listed as well for the convenience of backward compatibility.

Equation 7.

Equation 8.

where

• P_D is the power dissipation shown in Equation 4 and Equation 5.
• T_T is the temperature at the center-top of the IC package.
• T_B is the PCB temperature measured 1-mm away from the thermal pad package on the PCB surface (see Figure 32).

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Figure 31. Recommended Land Pad Pattern

Figure 32. Package Thermal Measurement