7.3.12 REFOUT (V_REF) Consideration for DDR2 Applications

During TPS51200 tracking start-up, the REFIN voltage follows the rise of the VDDQ rail through a voltage divider, and REFOUT (V_REF) follows REFIN once the REFIN voltage is greater than 0.39 V. When the REFIN voltage is lower than 0.39 V, V_REF is 0 V.

The JEDEC DDR2 SDRAM Standard (JESD79-2E) states that V_REF must track VDDQ/2 within ±0.3 V accuracy during the start-up period. To allow the TPS51200

device to meet the JEDEC DDR2 specification, a resistor divider can be used to provide the V_REF signal to the DIMM. The resistor divider ratio is 0.5 to ensure that the V_REF voltage equals VDDQ/2.

Figure 23. Resistor Divider Circuit

When selecting the resistor value, consider the impact of the leakage current from the DIMM V_REF pin on the reference voltage. Use Equation 4 to calculate resistor values.

Equation 4.

where

• R_REF is the resistor value
• ∆V_REF is the V_REF DC variation requirement
• I_REF is the maximum total V_REF leakage current from DIMMs

Consider the MT47H64M16 DDR2 SDRAM component from Micron as an example. The MT47H64M16 datasheet shows the maximum V_REF leakage current of each DIMM is ±2 µA, and V_REF(DC) variation must be within ±1% of VDDQ. In this DDR2 application, the VDDQ voltage is 1.8 V. Assuming one TPS51200 device needs to power 4 DIMMs, the maximum total V_REF leakage current is ±8 µA. Based on the calculations, the resistor value should be lower than 4.5 kΩ. To ensure sufficient margin, 100 Ω is the suggested resistor value. With two 100-Ω resistors, the maximum V_REF variation is 0.4 mV, and the power loss on each resistor is 8.1 mW.