SLUSDW9A June 2020 – June 2020 TPS51215A
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Switch Mode Power Supply Control
- 7.3.2 VREF, V0, V1, V2, V3 and Output Voltage
- 7.3.3 Soft-Start and Power Good
- 7.3.4 SLEW and VID Function
- 7.3.5 MODE Pin Configuration
- 7.3.6 Light-Load Operation
- 7.3.7 Out-of-Bound Operation
- 7.3.8 Current Sensing and Overcurrent Protection
- 7.3.9 Overvoltage and Undervoltage Protection
- 7.3.10 V5IN Undervoltage Lockout Protection
- 7.3.11 Thermal Shutdown
- 7.4 D-CAP2 Control Mode
- 8 Application and Implementation
-
9 Typical Applications
- 9.1 Design Requirements
- 9.2
Detailed Design Procedure
- 9.2.1 Step One: Determine the Specifications
- 9.2.2 Step Two: Determine System Parameters
- 9.2.3 Step Three: Determine Inductor Value and Choose Inductor
- 9.2.4 Step Four: Set the Output Voltages
- 9.2.5 Step Five: Calculate SLEW Capacitance
- 9.2.6 Step Six
- 9.2.7 Step Seven: Determine the Output Capacitance
- 9.2.8 Step Eight: Select Decoupling and Peripheral Components
- 9.3 Application Examples
- 9.4 Application Curves of Design 1
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
9.2.7 Step Seven: Determine the Output Capacitance
The switching frequency for D-CAP2 mode is 600 kHz and it is generally recommend to have a unity gain crossover (f0) of 1/4 of the switching frequency, which is approximately 150kHz for the purpose of this application.
Given the range of the recommended unity gain frequency, the power stage design is flexible, as long as the LC double pole frequency is less than 10% of f0.
As long as the LC double pole frequency is designed to be less than 1/10 of f0, the internal compensation network provides sufficient phase boost at the unity gain crossover frequency in order for the converter to be stable with enough margin.
When the ESR frequency of the output bulk capacitor is in the vicinity of the unity gain crossover frequency of the loop, additional phase boost is achieved. This applies to POSCAP and/or SPCAP output capacitors.
When the ESR frequency of the output capacitor is beyond the unity gain crossover frequency of the loop, no additional phase boost is achieved. This applies to low/ultra low ESR output capacitors, such as MLCCs.
Equation 11 and Equation 12 can be used to estimate the amount of capacitance needed for a given dynamic load step/release. Note that there are other factors that may impact the amount of output capacitance for a specific design, such as ripple and stability. Equation 11 and Equation 12 are used only to estimate the transient requirement, the result should be used in conjuction with other factors of the design to determine the necessary output capacitance for the application.
Equation 11 and Equation 12 calculate the minimum COUT for meeting the transient requirement, which is 480 µF assuming ±7.5% voltage allowance for load step and release.