TI recommends a four-layer PCB for good thermal performance and with maximum ground plane. 3-inch × 3-inch, four-layer PCB with 2-oz copper is used as example.
Place the decoupling capacitors right across VIN and VCC as close as possible.
Place output inductor and capacitors with IC at the same layer, SW routing should be as short as possible to minimize EMI, and should be a width plane to carry big current, enough vias should be added to the GND connection of output capacitor and also as close to the output pin as possible.
Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace is recommended to reduce line parasitic inductance.
Feedback could be 20 mil and must be routed away from the switching node, BST node or other high efficiency signal.
VIN trace must be wide to reduce the trace impedance and provide enough current capability.
Place multiple vias under the device near VIN and GND and near input capacitors to reduce parasitic inductance and improve thermal performance