The device detects the voltage on the MODE pin during start-up and latches onto one of the MODE options listed in Table 7-1. The voltage on the MODE pin is recommended to be set by connecting this pin to the center tap of a resistor divider connected between VCC and AGND. A guideline for the top resistor (R_{M_H}) and the bottom resistor (R_{M_L}) as 1% resistors is shown in Table 7-1. It is recommended to choose the resistor to set the voltage at around the middle value of each range. It is important that the voltage for the MODE pin is derived from the VCC rail only since internally this voltage is referenced to detect the MODE option, and not to leave the mode pin floating. The MODE pin setting can be reset only by a VIN power cycling or EN toggle.

Figure 7-1 shows the typical start-up sequence of the device once the enable signal crosses the EN turnon threshold. After the voltage on VCC crosses the rising UVLO threshold, it takes about 500 μs to finish the working mode and frequency selection. The output voltage starts ramping after about 0.2*T_SS delay time.

Figure 7-1 Power-Up Sequence