ZHCSJ77F December 2010 – December 2018 TPS51916
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 VDDQ Switch Mode Power Supply Control
- 7.3.2 VREF and REFIN, VDDQ Output Voltage
- 7.3.3 Soft-Start and Powergood
- 7.3.4 Power State Control
- 7.3.5 Discharge Control
- 7.3.6 VTT and VTTREF
- 7.3.7 VDDQ Overvoltage and Undervoltage Protection
- 7.3.8 VDDQ Out-of-Bound Operation
- 7.3.9 VDDQ Overcurrent Protection
- 7.3.10 VTT Overcurrent Protection
- 7.3.11 V5IN Undervoltage Lockout Protection
- 7.3.12 Thermal Shutdown
- 7.4 Device Functional Modes
- 7.5 D-CAP2™ Mode Operation
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文档支持
- 12机械、封装和可订购信息
7.3.3 Soft-Start and Powergood
Provide a voltage supply to VIN and V5IN before asserting S5 to high. TPS51916 device provides integrated VDDQ soft-start functions to suppress in-rush current at start-up. The soft-start is achieved by controlling internal reference voltage ramping up. Figure 34 shows the start-up waveforms. The switching regulator waits for 400μs after S5 assertion. The MODE pin voltage is read in this period. A typical VDDQ ramp up duration is 700μs.
TPS51916 device has a powergood open-drain output that indicates the VDDQ voltage is within the target range. The target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay for assertion (low to high), and ±16% (typ) and 330-ns delay for de-assertion (high to low) during running. The PGOOD start-up delay is 2.5 ms after S5 is asserted to high. Note that the time constant which is composed of the REFIN capacitor and a resistor divider needs to be short enough to reach the target value before PGOOD comparator enabled.
Figure 34. Typical Start-up Waveforms