7.4.2 D-CAP™ Mode

Figure 36 shows a simplified model of D-CAP™ mode architecture.

Figure 36. Simplified D-CAP™ Model

The VDDQSNS voltage is compared with REFIN voltage. The PWM comparator creates a set signal to turn on the high-side MOSFET. The gain and speed of the comparator is high enough to maintain the voltage at the beginning of each on-cycle (or the end of each off-cycle) to be substantially constant. The DC output voltage monitored at VDDQ may have line regulation due to ripple amplitude that slightly increases as the input voltage increase. The D-CAP™ mode offers flexibility on output inductance and capacitance selections with ease-of-use without complex feedback loop calculation and external components. However, it does require a sufficient level of ESR that represents inductor current information for stable operation and good jitter performance. Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended.

The requirement for loop stability is simple and is described in Equation 3. The 0-dB frequency, f₀ defined in Equation 3, is recommended to be lower than 1/3 of the switching frequency to secure proper phase margin.

Equation 3.

where

• ESR is the effective series resistance of the output capacitor
• C_OUT is the capacitance of the output capacitor
• f_sw is switching frequency

Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that determine jitter performance in D-CAP™ mode is the down-slope angle of the VDDQSNS ripple voltage. Figure 37 shows, in the same noise condition, that jitter is improved by making the slope angle larger.

Figure 37. Ripple Voltage Slope and Jitter Performance

For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period as shown in Figure 37 and Equation 4.

Equation 4.

where

• V_OUT is the VDDQ output voltage
• L_X is the inductance