7.3.9 Power Good

The TPS53219A has a power-good output that indicates high when switcher output is within the target. The power-good function is activated after soft-start has finished. If the output voltage becomes within +10% or –5% of the target value, internal comparators detect power-good state and the power-good signal becomes high after a 1-ms internal delay. If the output voltage goes outside of +15% or –10% of the target value, the power-good signal becomes low after two microsecond (2-µs) internal delay. The power-good output is an open-drain output and must be pulled up externally.

In order for the PGOOD logic to be valid, the VDD input must be higher than 1 V. To avoid invalid PGOOD logic before the TPS53219A is powered up, TI recommends that the PGOOD pin be pulled up to VREG (either directly or through a resistor divider if a different pullup voltage is desired) because VREG remains low when the device is powered off. The pullup resistance can be chosen from a standard resistor value between 1 kΩ and 100 kΩ.