ZHCSTR3B December   2010  – November 2023 TPS53315

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  D-CAP™ Integrated Circuit with Adaptive On-Time
      2. 6.3.2  Small Signal Model
      3. 6.3.3  Ramp Signal
      4. 6.3.4  Auto-Skip Eco-mode Light Load Operation
      5. 6.3.5  Adaptive Zero Crossing
      6. 6.3.6  Forced Continuous Conduction Mode
      7. 6.3.7  Power Good
      8. 6.3.8  Current Sense and Overcurrent Protection
      9. 6.3.9  Overvoltage and Undervoltage Protection
      10. 6.3.10 UVLO Protection
      11. 6.3.11 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Enable and Soft Start
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Circuit Diagram
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Step 1: Select Operation Mode and Soft-Start Time
          2. 7.2.1.2.2 Step 2: Select Switching Frequency
          3. 7.2.1.2.3 Step 3: Select the Inductance
          4. 7.2.1.2.4 Step 4: Select Output Capacitors
          5. 7.2.1.2.5 Step 5: Determine the Voltage-Divider Resistance (R1 and R2)
          6. 7.2.1.2.6 Step 6: Select the Overcurrent Resistance (RTRIP)
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Typical Application Circuit Diagram With Ceramic Output Capacitors
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Step 1: Select Operation Mode and Soft-Start Time
          2. 7.2.2.2.2 Step 2: Select Switching Frequency
          3. 7.2.2.2.3 Step 3: Select the Inductance
          4. 7.2.2.2.4 Step 4: Select Output Capacitance for Ceramic Capacitors
          5. 7.2.2.2.5 Step 5: Select the Overcurrent Setting Resistance (RTRIP)
        3. 7.2.2.3 External Component Selection When Using All Ceramic Output Capacitors
        4. 7.2.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Overview

The TPS53315 is a high-efficiency, single channel, synchronous buck converter designed for low output voltage point-of-load applications in computing and similar digital consumer applications. The device features proprietary D-CAP integrated circuit combined with an adaptive on-time architecture. This combination is designed for building modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage range is from 3 V up to 15 V. The D-CAP integrated circuit uses the ESR of the output capacitors to sense the device current. One advantage of this control scheme is that this control scheme does not require an external phase compensation network. This allows a simple design with a low external component count. Eight preset switching frequency values can be chosen using a resistor connected from the RF pin to ground or the VREG pin. Adaptive on-time control tracks the preset switching frequency over a wide input and output voltage range while allowing the switching frequency to increase at the step-up of the load.

The TPS53315 has a MODE pin to select between auto-skip mode and forced continuous conduction mode (FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to 5.6 ms.