ZHCS609A December   2011  – November 2016 TPS53316

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Overcurrent and Frequency Setting
      2. 7.3.2 Soft-Start Operation
      3. 7.3.3 Power Good
      4. 7.3.4 UVLO Function
      5. 7.3.5 Overcurrent Protection
      6. 7.3.6 Overvoltage Protection
      7. 7.3.7 Undervoltage Protection
      8. 7.3.8 Overtemperature Protection
      9. 7.3.9 Output Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
      2. 7.4.2 Light Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Determine the Value of R1 and R2
        2. 8.2.2.2 Choose the Inductor
        3. 8.2.2.3 Choose the Output Capacitor(s)
        4. 8.2.2.4 Choose the Input Capacitors
        5. 8.2.2.5 Compensation Design
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

RGT Package
16-Pin QFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 EN I Enable pin. Internally pulled-up to the VIN pin through a 2-MΩ resistor. The EN voltage must be less than (VIN + 0.5 V).
2 RF/OC I Switching frequency and OC level configuration pin:
Connecting to ground: 1.1 MHz, 6.5-A OCP
Pulled high or floating (internal pulled high): 1.1 MHz, 4.5-A OCP
Connect with 24.3 kΩ to GND: 750 kHz, 4.5-A OCP
Connect with 57.6 kΩ to GND: 750 kHz, 6.5-A OCP
Connect with 105 kΩ to GND: 2 MHz, 4.5-A OCP
Connect with 174 kΩ to GND: 2 MHz, 6. 5-A OCP
3 PGD O Power good output flag. Open-drain output. Pull up to an external rail through a resistor.
4 VBST P Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW terminal.
5 SW B Output inductor connection to integrated power devices
6 SW B Output inductor connection to integrated power devices
7 SW B Output inductor connection to integrated power devices
8 PS I Mode configuration pin (with10-µA current):
Connecting to ground: Forced CCM with 4x softstart time
Pulled high or floating (internal pulled high): Forced CCM master
Connect with 24.3 kΩ to GND: HEF mode with 4x softstart time
Connect with 57.6 kΩ to GND: HEFF mode
Connect with 105 kΩ to GND: DE mode
Connect with 174 kΩ to GND: DE mode with 4x softstart time
9 COMP O Error amplifier compensation terminal. Type III compensation method is generally recommended for stability.
10 FB I Voltage feedback pin. Use for OVP, UVP, and PGD determination.
11 AGND G Device analog ground terminal
12 VREG3 O 3.3-V LDO output, serves as supply voltage for internal analog circuitry. The EN pin controls the turnon function of the LDO.
13 VIN P Gate driver supply and power conversion input voltage. The input range is from 2.9 V to 6 V.
14 VIN P Gate driver supply and power conversion input voltage. The input range is from 2.9 V to 6 V.
15 PGND P Device power ground terminal
16 PGND P Device power ground terminal
— PowerPad — Thermal pad of the device. Use 4 or 5 vias to connect to GND plane for heat dissipation.
(1) B = Bidirectional, G = Ground, I = Input, O = Output, P = Supply
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