ZHCS979F June   2012  – October 2020 TPS53318 , TPS53319

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
    7. 7.7 TPS53319 Typical Characteristics
    8. 7.8 TPS53318 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  5-V LDO and VREG Start-Up
      2. 8.3.2  Adaptive On-Time D-CAP Control and Frequency Selection
      3. 8.3.3  Ramp Signal
      4. 8.3.4  Adaptive Zero Crossing
      5. 8.3.5  Output Discharge Control
      6. 8.3.6  Power-Good
      7. 8.3.7  Current Sense, Overcurrent, and Short Circuit Protection
      8. 8.3.8  Overvoltage and Undervoltage Protection
      9. 8.3.9  Redundant Overvoltage Protection (OVP)
      10. 8.3.10 UVLO Protection
      11. 8.3.11 Thermal Shutdown
      12. 8.3.12 Small Signal Model
      13. 8.3.13 External Component Selection Using All Ceramic Output Capacitors
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable, Soft Start, and Mode Selection
      2. 8.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 8.4.3 Forced Continuous Conduction Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Using Bulk Output Capacitors, Redundant Overvoltage Protection Function (OVP) Disabled
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Step One: Select Operation Mode and Soft-Start Time
          2. 9.2.1.2.2 Step Two: Select Switching Frequency
          3. 9.2.1.2.3 Step Three: Choose the Inductor
          4. 9.2.1.2.4 Step Four: Choose the Output Capacitor or Capacitors
          5. 9.2.1.2.5 Step Five: Determine the Value of R1 and R2
          6. 9.2.1.2.6 Step Six: Choose the Overcurrent Setting Resistor
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application Using Ceramic Output Capacitors, Redundant Overvoltage Protection Function (OVP) Enabled
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 External Component Selection Using All Ceramic Output Capacitors
          2. 9.2.2.2.2 Redundant Overvoltage Protection
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

GUID-FA69D7C5-0877-4265-88DB-22D69D9C2A9D-low.gif Figure 6-1 22 Pins DQP (LSON-CLIP) Package (Top View)
Table 6-1 Pin Functions
PIN I/O/P(1) DESCRIPTION
NAME NO.
EN 2 I Enable pin. Typical turnon threshold voltage is 1.3 V. Typical turnoff threshold voltage is 1.0 V.
GND G Ground and thermal pad of the device. Use proper number of vias to connect to ground plane.
LL 6 B Output of converted power. Connect this pin to the output inductor.
7
8
9
10
11
MODE 20 I Soft start and mode selection. Connect a resistor to select soft-start time using Table 8-3. The soft-start time is detected and stored into internal register during start-up.
PGOOD 3 O Open drain power-good flag. Provides 1-ms start-up delay after VFB falls in specified limits. When VFB goes out of the specified limits, PGOOD goes low after a 2-µs delay.
ROVP 5 I Redundant overvoltage protection (OVP) input. Use a resistor divider to connect this pin to VOUT. Internally pulled down to GND with a 1.5-MΩ resistor. If redundant OVP is not needed, connect this pin to GND. Do not leave ROVP pin floating (see Section 8.3.9).
RF 22 I Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using Table 8-1. The switching frequency is detected and stored during the start-up.
TRIP 21 I OCL detection threshold setting pin. ITRIP = 10 µA at room temperature. 3000 ppm/°C current is sourced and set the OCL trip voltage as follows.
VOCL = VTRIP/32 (VTRIP ≤ 2.4 V, VOCL ≤ 75 mV)
VBST 4 P Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL node. Internally connected to VREG via bootstrap MOSFET switch.
VDD 19 P Controller power supply input. VDD input voltage range is from 4.5 V to 25 V.
VFB 1 I Output feedback input. Connect this pin to VOUT through a resistor divider.
VIN 12 P Conversion power input. The conversion input voltage range is from 1.5 V to 22 V.
13
14
15
16
17
VREG 18 P 5-V low dropout (LDO) output. Supplies the internal analog circuitry and driver circuitry.
Thermal Pad G Ground and thermal pad of the device. Use a proper number of vias to connect to ground plane.
(1) I = Input, O = Output, B = Bidirectional, P = Supply, G = Ground
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |