ZHCS979F June   2012  – October 2020 TPS53318 , TPS53319

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
    7. 7.7 TPS53319 Typical Characteristics
    8. 7.8 TPS53318 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  5-V LDO and VREG Start-Up
      2. 8.3.2  Adaptive On-Time D-CAP Control and Frequency Selection
      3. 8.3.3  Ramp Signal
      4. 8.3.4  Adaptive Zero Crossing
      5. 8.3.5  Output Discharge Control
      6. 8.3.6  Power-Good
      7. 8.3.7  Current Sense, Overcurrent, and Short Circuit Protection
      8. 8.3.8  Overvoltage and Undervoltage Protection
      9. 8.3.9  Redundant Overvoltage Protection (OVP)
      10. 8.3.10 UVLO Protection
      11. 8.3.11 Thermal Shutdown
      12. 8.3.12 Small Signal Model
      13. 8.3.13 External Component Selection Using All Ceramic Output Capacitors
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable, Soft Start, and Mode Selection
      2. 8.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 8.4.3 Forced Continuous Conduction Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Using Bulk Output Capacitors, Redundant Overvoltage Protection Function (OVP) Disabled
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Step One: Select Operation Mode and Soft-Start Time
          2. 9.2.1.2.2 Step Two: Select Switching Frequency
          3. 9.2.1.2.3 Step Three: Choose the Inductor
          4. 9.2.1.2.4 Step Four: Choose the Output Capacitor or Capacitors
          5. 9.2.1.2.5 Step Five: Determine the Value of R1 and R2
          6. 9.2.1.2.6 Step Six: Choose the Overcurrent Setting Resistor
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application Using Ceramic Output Capacitors, Redundant Overvoltage Protection Function (OVP) Enabled
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 External Component Selection Using All Ceramic Output Capacitors
          2. 9.2.2.2.2 Redundant Overvoltage Protection
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout Guidelines

  • The power components (including input/output capacitors, inductor, and TPS53318 or TPS53319 device) should be placed on one side of the PCB (solder side). At least one inner plane should be inserted, connected to ground, to shield and isolate the small signal traces from noisy power lines.
  • All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE, and RF should be placed away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer or layers as ground plane or planes and shield feedback trace from power traces and components.
  • Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC current loop.
  • Because the TPS53319 device controls output voltage referring to voltage across the VOUT capacitor, the top-side resistor of the voltage divider should be connected to the positive node of the VOUT capacitor. The GND of the bottom side resistor should be connected to the GND pad of the device. The trace from these resistors to the VFB pin should be short and thin.
  • Place the frequency setting resistor (RF), OCP setting resistor (RTRIP), and mode setting resistor (RMODE) as close to the device as possible. Use the common GND via to connect them to GND plane if applicable.
  • Place the VDD and VREG decoupling capacitors as close to the device as possible. Ensure to provide GND vias for each decoupling capacitor and make the loop as small as possible.
  • For better noise filtering on VDD, a dedicated and localized decoupling support is strongly recommended.
  • The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor, should be as short and wide as possible.
  • Connect the ripple injection VOUT signal (VOUT side of the C1 capacitor in Figure 9-12) from the terminal of ceramic output capacitor. The AC coupling capacitor (C2 in Figure 9-12) should be placed near the device, and R7 and C1 can be placed near the power stage.
  • Use separated vias or trace to connect LL node to snubber, boot strap capacitor, and ripple injection resistor. Do not combine these connections.