The TPS53676 device is designed to be
compatible with the timing and physical layer electrical characteristics of the
Power Management Bus (PMBus) Specification, part III (AVSBus) revision 1.3.1
available at http://pmbus.org. AVS_VDDIO and logic levels of 1.14 V to (VCC pin
voltage, 3.6 V maximum) are supported. Clock operation up to 50 MHz is supported.
TPS53676 requires approximately 14 ns (maximum) from a clock edge to a transition of
the AVS_SDATA pin, and at very high-frequency operation, it may be necessary to
increase the clock high time (thigh) to compensate. Refer to the
technical reference manual for more information.
The AVSBus communication interface is similar to the de-facto Serial
Peripheral Interface (SPI) standard with the following configuration:
- No chip select (CSO#) pin is
used. AVSBus is a point-to-point protocol.
- AVS_CLK idles LOW
- AVS_MDATA and AVS_SDATA idle
HIGH
- A transmitter launches data
on the rising edge of AVS_CLK
- A receiver captures data on
the falling edge of AVS_CLK
- MSB transmitted first
Refer to to the PMBus specification revision 1.3.1, part III for more
information.
To enable AVSBus control in the
device:
- Ensure the AVSBUS EN CHA / AVSBUS EN CHB options in the MISC_OPTIONS PMBus
command are set to 1b in NVM.
- Set the value of VOUT SRC CHA / VOUT SRC CHB to 10b in NVM. This setting in
itself only sets the default value of the OPERATION command bits 5:2.
- Set the OPERATION[5:2] bits to 1100b to hand-off output voltage control to the
AVSBus Interface.
Note: Transferring output voltage control
from PMBus to AVSBus during power conversion causes the output voltage to transition
to a low value, until the host issues the next AVSBus voltage command. Internal
architecture limitations determine this behavior. As a result, while output voltage
control may be changed without a power cycle, TI recommends that changes between
PMBus and AVSBus control occur without power conversion being active.