Figure 7-12 illustrates how to interface the TPS53676 with a host ASIC or load with an integrated Serial Peripheral Interface (SPI) port. AVSBus is a point-to-point protocol and does not use a chip select (CS) pin. AVSBus uses push-pull signaling and requires a separate supply pin, AVS_VDDIO. Connect a well-regulated supply bewteen 1.14 V and 3.6 V to AVS_VDDIO, and a local high quality ceramic bypass capacitor of 100 nF minimum effective capacitance. The input high and low thresholds are set relative to the voltage supplied at the AVS_VDDIO pin, as shown in the Electrical Specifications table. In applications which do not use AVSBus, ground the AVS_VDDIO, AVS_CLK and AVS_MDATA pins; float the AVS_SDATA pin.

AVSBus communication can be run at up to 50 MHz clock rate, and may require special care in PCB routing for signal integrity. Note the TPS53676 device has a clock-to-output delay of up to 14 ns, which exceeds the half-clock cycle setup time nominally given to an AVSBus slave at the full 50 MHz clock rate. This may require changing the duty cycle of the clock to compensate, as described in the AVSBus specification. Refer to the PMBus specification revision 1.3.1, part III for more information about AVSBus.

Figure 7-12 AVSBus connection diagram