Use the PHASE_CONFIG command to assign each PWM pin to a logical phase number.
Refer to the Technical Reference Manual for a register map of the PHASE_CONFIG command. Each PWM pin has 4 available settings:
- ENABLE: Controls whether the phase is active or remains at tristate always.
- PAGE: Assigns each phase to channel A or channel B. This setting also determines which CSP pins are incorporated in the ISUM control signals for each channel.
- PHASE: Assigns each phase within a channel a PHASE setting at which it can be addressed. Note the PHASE assignment is not backed by non-volatile memory, and each phase is assigned a derived PHASE setting at power-on.
- ORDER: Controls the order in which phases are fired with respect to each other. Figure 7-15 and Figure 7-16 illustrate the effect of different ordering assignments. Reconfigure the phase ordering to ensure adjacent phases do not interfere with each other due to layout related coupling issues. If dynamic phase shedding is used, phases add or drop according to their assigned ORDER value.
Figure 7-15 0-1-2-3-4-5 fire order (6 phase example) Figure 7-16 0-2-4-1-3-5 fire order (6 phase example) Observe the following rules when updating the phase configuration settings. The Fusion Digital Power Designer GUI enforces these rules, but the controller itself does not:
- Channel A may be assigned up to 7 phases. Channel B may be assigned up to 3 phases.
- The ORDER assignments within a channel must be continuous, and start at 0. Do not skip phase order assignments.
- The PHASE assignments within a channel must be continuous, start at 0 counting upward from APWM1 for channel A and downward from BPWM1 for channel B.
Example: 3+2 phase configuration with
non-standard fire order
- Disable power conversion, as specified per
ON_OFF_CONFIG.
- Write the PHASE_CONFIG command as shown below.
- Issue STORE_DEFAULT_ALL to save the current settings into NVM as default values
for the next power-on.
Table 7-7 Example settings: 3+2Physical Phase | Enable | Page | Phase | Order |
---|
Pins 12, 27 (APWM1) | 1 | 0 | 0 | 0 |
Pins 11, 28 (APWM2) | 1 | 0 | 1 | 2 |
Pins 10, 29 (APWM3) | 1 | 0 | 2 | 1 |
Pins 9, 30 (APWM4) | 0 | x | x | x |
Pins 8, 31 (APWM5/BPWM3) | 0 | x | x | x |
Pins 7, 32 (APWM6/BPWM2) | 1 | 1 | 1 | 1 |
Pins 6, 33 (APWM7/BPWM1) | 1 | 1 | 0 | 0 |
Pins 5, 34 (NC) | 0 | x | x | x |
Pins 4, 35 (NC) | 0 | x | x | x |
Pins 3, 36 (NC) | 0 | x | x | x |
Pins 2, 37 (NC) | 0 | x | x | x |
Pins 1, 37 (NC) | 0 | x | x | x |