The TPS53676 AVSBus status register
provides warning information only. During latch-off faults, and while power
conversion is disabled, TPS53676 does not respond to AVSBus transactions. The AVSBus
and PMBus status registers are independent. Clearing a warning condition through
AVSBus does not affect the PMBus status registers.
TPS53676 supports AVS_SDATA interrupt notification as defined in the AVSBus
specification. When any warning bit sets in the AVSBus status register, the device
pulls the AVS_SDATA line low to notify the host of the warning condition. The
AVS_SDATA line remains low until the host clears the condition through through a
write to the AVSBus status register.
Every AVS_SDATA frame contains a 5-bit summary (StatusResp) of the current device
status:
- Bit 4: VDONE - 1b if the output voltage has reached its commanded
target
- Bit 3: STATUS - 1b if any bits in the AVS Status register are set
- Bit 2: AVS CTRL - 1b AVSBus has control of the output voltage
- Bit 1: MFR_SPEC_1- Set to 1b if the RESET# pin function is LOW
- Bit 0: MFR_SPEC_0- Set to 0b always.
The TPS53676 AVSBus status register is defined as follows:
- Bit 15: VDONE - set to 1b if the output voltage has reached its commanded
target
- Bit 14: OCW - 1b if the output overcurrent warning has been latched
- Bit 13: UVW - 1b if the output undervoltage warning has been latched
- Bit 12: OTW - 1b if the output overtemperature warning has been
latched
- Bit 11: OPW - 0b always. Not supported by TPS53676.
- Bit 10:8: Reserved - 0b always.
- Bit 7: OVW - 1b if the output overvoltage warning has been latched
- Bit 6: MINMAX - 1b if the output min/max warning has been latched
- Bit 5: ISHARE - 1b if a current share warning has been latched
- Bit 4: PHOCL - 1b if a
per-phase OCL warning has been latched. Note this bit requires a PMBus
CLEAR_FAULT and AVSBus status write to clear.
- Bit 3: VIN OVW - 1b if a input overvoltage warning has been latched
- Bit 2: VIN UVW - 1b if a input undervoltage warning has been latched
- Bit 1: IIN OCW - 1b if a input overcurrent has been latched
- Bit 0: Reserved - 0b always.