10 Layout

Proper layout techniques are critical to power supply performance. The recommendations given in this document are meant to minimize risk and give the highest possibility of first pass success. Other layout designs are possible but may carry higher risk of performance issues. Contact your TI local field/sales representative for in-depth guidance and layout reviews.

The driverless controller architecture makes it easy to separate noisy driver interface lines from sensitive controller signals. Because the power stage is external to the device, all gate drive and switch node traces must be local to the inductor and power stages.

Controller Layout Guidelines

• Keep minimum 800 mil distance between the controller and the closest power stage
• Ensure the controller and all power stages must share a common ground plane
• Route CSPx /VREF differentially from controller to IOUT/REFIN pin of each power stages on a quiet inner layer. Alternately, create a small VREF copper plane between controller and power stages, and embed the CSPx traces inside VREF plane.
• PWMx must be routed on a different quiet inner layer and not on the same layer next to CSPx/VREF differential pairs.

Power stage layout guidelines

• Use the recommended land and via pattern for power stage footprint
• Make layer 2 on the PCB stack a solid ground plane
• Maximize the phase pitch between adjacent phases whenever possible to prevent any cross-coupling noise between devices (9 mm or higher is preferred)
• In cases where the phase pitch is tighter, adjust the controller phase firing order to minimize noise coupling between devices.
• The input voltage bypass capacitors require a minimum two vias per pad(for both Vin and GND)
• Place additional GND vias along the sides of device as space allows
• For multi-phase systems, ensure that the GND pour connects all phases.
• Connect the VOS pin feedback point to the inner edge of the inductor output pad.
• Place VDD and PVDD bypass capacitors directly next to pins on the same layer of the device.

Layout example

Figure 10-1 Controller layout example

Figure 10-2 CSP signal routing example

Figure 10-3 Power stage placement example