By default, pin 19 functions as the channel B enable pin, BVR_EN. Use the MULTIFUNCTION_PIN_CONFIG command to assign pin 19 as a synchronization pin as needed. When pin 19 is not assigned as BVR_EN, the AVR_EN pin becomes a shared enable pin for both channels. When there is no SYNC pin assigned, configure the SYNC_CONFIG to operate based on internal timing, in order to maintain an accurate switching frequency over the full range of operation. Any external clock applied to TPS53676 must have a 50% duty cycle, and the FREQUENCY_SWITCH command must still be programmed as close as possible to the desired switching frequency after any scaling. The input on the SYNC pin must be ±50 kHz from the configured FREQUENCY_SWITCH value.

An internal phase-locked loop (PLL) adjusting the on-time of each phase enables edge synchronization. During steady-state operation, when synchronization is used, the PWM pin assigned to order 0 is synchronized to a clock on the SYNC pin. The DCAP+ control topology is inherently a variable frequency scheme. During load transients, the pulse frequency of each channel modulates to maintain voltage regulation. Load transients cause the PLL to lose phase lock, and slowly return to phase lock based on the PLL loop bandwidth. The PLL bandwidth is much slower than the voltage regulation loop, and it can take many cycles for the PLL to re-lock following a transient event. Figure 7-8 illustrates the DCAP+ response to a load transient using edge synchronization.

Figure 7-8 Synchronization behavior (2 phase example, no phase shift)

The SYNC_CONFIG command configures various options related to synchronization. These include: enable/disable of the PLL, sync direction (clock master or clock slave), input clock division ratio, phase shift, and gain/scalar terms to increase/decrease the PLL loop bandwidth. Refer to the Technical Reference Manual for a complete register map.

Figure 7-9 and Figure 7-10 illustrate two common methods of synchronizing multiple converters based on TPS53676. Use the programmable phase shift parameters to phase spread multiple converters, to improve ripple cancellation and reduce beat frequencies on input supplies.

Figure 7-9 Clock master driving a clock slave

Figure 7-10 Two clock slaves driven externally