ZHCSN24A August 2019 – May 2021 TPS53676
PRODUCTION DATA
The TPS53676 does not have strict power sequencing requirements. The VCC supply, power stage VDD 5V supply, VIN_CSNIN and CSPIN supplies may be safely powered up independently of each other, even if the VCC supply voltage is off and low-impedance. Do not raise pull-up voltages for open-drain pins AVR_RDY, BVR_RDY, SMB_ALRT#, SMB_DIO, VR_FAULT# before the VCC supply, or pull them to voltages above the VCC voltage during operation. Similarly, it is not recommended to pull the AVS_VDDIO supply above VCC, or pull the AVS_CLK, AVS_MDATA, AVS_SDATA pins above AVS_VDDIO. If system sequencing requirements mandate raising the pull-up voltages for these pins prior to VCC being established, limit the pin current to 1.0 mA to avoid damage to the device.
The minimum pull-up resistor value for open drain pins AVR_RDY, BVR_RDY, SMB_ALRT#, SMB_DIO, VR_FAULT# is limited by the allowable sinking current for the pin. The maximum pull-up resistor value is limited by the off-state leakage current for the pin, and the logic level of any downstream device using the pin as an input. The table below summarizes the allowable sinking current and off-state leakage for open drain IO pins.
| Open-drain Pin | Maximum Current | |
|---|---|---|
| On-state Sinking (mA) |
Off-state leakage 1 (μA) |
|
| AVR_RDY | 25.0 | 1.0 |
| BVR_RDY | 25.0 | 1.0 |
| SMB_ALRT# | 20.0 | 1.0 |
| SMB_DIO | 20.0 | 1.0 |
| VR_FAULT# | 20.0 | 4.0 |
For input pins ACSPx, BCSPx, AVR_EN, BVR_EN, SYNC, RESET#, which exceed the VCC pin value during operation, during power-on or otherwise, include a series resistor of 10.0 kΩ or greater to limit the current into the pin.
It is safe to power-on the VDD 5V supply to TI smart power stage devices prior to TPS53676 VCC. TI smart power stage devices do not source any unsafe voltages or currents into TPS53676 ACSPx, BCSPx, ATSEN, BTSEN, APWMx, BPWMx pins when the VCC pin is not powered.
TI smart power stages (CSD95xxx) provide hysteresis current on their PWM input pins to improve noise immunity. This current is active when the power stage is powered by 5V VDD and enabled, regardless of the status of VCC. When the VCC pin of TPS53676 is unpowered, this hysteresis current flows through the PWM pins, to ESD structures in the controller, causing the PWM pin voltage to float low, out of the tri-state window. This can cause the power stage device to switch its low-side power MOSFET on. As a result, in any case where the power stage VDD 5V power supply is enabled prior to VCC, supply, TI recommends to control the power stage enable pin to be low until both supply voltages are established.
TPS53676 voltage and current protections become active when the controller VCC supply is powered. TI recommends the VCC voltage be powered first, prior to power stage 5V, or VIN_CSNIN/CSPIN voltages. In general, TI recommends to assert the AVR_EN/BVR_EN pins last in the power sequence.
Other sequences are permissible, but may not be able to make use of the controller protection features. For example, if a board assembly issue causes the power input supply (e.g. nominally 12V supply) to charge the output voltage, the TPS53676 over-voltage protection can protect the load device by forcing the PWM pins low, causing the power stage devices to discharge the output voltage, but only if the VCC supply is established by the time the power input voltage rises.