米6体育平台手机版

ZHCSN24A August 2019 – May 2021 TPS53676

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6.4.11 Phase-Locked Loop and Closed-Loop Frequency Control

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J = -40 to 125 ℃ unless otherwise specified

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Switching Frequency
f_SW(RNG)	Switching Frequency Range	V_IN = 12 V, V_VSP = 1.0 V f_SW × N_Φ ≤ 8 MHz	300		2000	kHz
f_SW(TOL)	Switching Frequency Tolerance	V_IN = 12 V, V_VSP = 1.0 V f_SW × N_Φ ≤ 8 MHz	–10		10	%
Phase-Lock Loop and Synchronization
V_IL(SYNC)	SYNC input logic low ⁽¹⁾				0.8	V
V_IH(SYNC)	SYNC input logic high ⁽¹⁾		1.35			V
V_OL(SYNC)	SYNC output logic low ⁽¹⁾	I_PIN = ± 0.5 mA			0.4	V
V_OH(SYNC)	SYNC output logic high ⁽¹⁾	I_PIN = ± 0.5 mA	1.7			V
t_PW(SYNC)	SYNC input minimum pulse width ⁽¹⁾		100			ns
D_SYNCOUT	SYNC output duty cycle ⁽¹⁾		40	50	60	%
f_SYNC	Synchronization frequency ⁽¹⁾		200		2000	kHz
Df_SYNC	SYNC allowable frequency difference from free-running frequency ⁽¹⁾	FREQUENCY_SWITCH from 300 kHz to 2 MHz	–50		50	kHz
M_SYNCA	Channel A Sync mode ⁽¹⁾	MFR_SPECIFIC_E4[5] = X MFR_SPECIFIC_E4[8] = 0b MFR_SPECIFIC_E4[14] = 0b	Disabled
		MFR_SPECIFIC_E4[5] = 0b MFR_SPECIFIC_E4[8] = 1b MFR_SPECIFIC_E4[14] = 0b	Internal Clock, CLF Mode
		MFR_SPECIFIC_E4[5] = 1b MFR_SPECIFIC_E4[8] = 0b MFR_SPECIFIC_E4[14] = 1b	External Clock, PLL Mode
M_SYNCB	Channel B Sync mode ⁽¹⁾	MFR_SPECIFIC_E4[6] = X MFR_SPECIFIC_E4[9] = 0b MFR_SPECIFIC_E4[15] = 0b	Disabled
		MFR_SPECIFIC_E4[6] = 0b MFR_SPECIFIC_E4[9] = 1b MFR_SPECIFIC_E4[15] = 0b	Internal Clock, CLF Mode
		MFR_SPECIFIC_E4[6] = 1b MFR_SPECIFIC_E4[9] = 0b MFR_SPECIFIC_E4[15] = 1b	External Clock, PLL Mode
PH_SYNCA	Channel A SYNC Phase Offset ⁽¹⁾	MFR_SPECIFIC_E4[23:20] = 0h		0		deg
		MFR_SPECIFIC_E4[23:20] = 1h		30		deg
		MFR_SPECIFIC_E4[23:20] = 2h		60		deg
		MFR_SPECIFIC_E4[23:20] = 3h		90		deg
		MFR_SPECIFIC_E4[23:20] = 4h		120		deg
		MFR_SPECIFIC_E4[23:20] = 5h		150		deg
		MFR_SPECIFIC_E4[23:20] = 6h		180		deg
		MFR_SPECIFIC_E4[23:20] = 7h		210		deg
		MFR_SPECIFIC_E4[23:20] = 8h		240		deg
		MFR_SPECIFIC_E4[23:20] = 9h		270		deg
		MFR_SPECIFIC_E4[23:20] = Ah		300		deg
		MFR_SPECIFIC_E4[23:20] = Bh		330		deg
PH_SYNCB	Channel B SYNC Phase Offset ⁽¹⁾	MFR_SPECIFIC_E4[31:28] = 0h		0		deg
		MFR_SPECIFIC_E4[31:28] = 1h		30		deg
		MFR_SPECIFIC_E4[31:28] = 2h		60		deg
		MFR_SPECIFIC_E4[31:28] = 3h		90		deg
		MFR_SPECIFIC_E4[31:28] = 4h		120		deg
		MFR_SPECIFIC_E4[31:28] = 5h		150		deg
		MFR_SPECIFIC_E4[31:28] = 6h		180		deg
		MFR_SPECIFIC_E4[31:28] = 7h		210		deg
		MFR_SPECIFIC_E4[31:28] = 8h		240		deg
		MFR_SPECIFIC_E4[31:28] = 9h		270		deg
		MFR_SPECIFIC_E4[31:28] = Ah		300		deg
		MFR_SPECIFIC_E4[31:28] = Bh		330		deg

(1) Specified by Design.

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6.4.11 Phase-Locked Loop and Closed-Loop Frequency Control