Table 2. Design Parameters

8.2.2.1 Switching Frequency

The first step is to decide on a switching frequency for the regulator. Typically, the user may want to choose the highest switching frequency possible, because this produces the smallest solution size. The high switching frequency allows for lower-valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. Alternatively, the user may choose a lower switching frequency to improve efficiency. At lower switching frequencies, switching losses are minimized. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage, the output voltage, and the frequency shift limitation.

Equation 10 and Equation 11 must be used to find the maximum switching frequency for the regulator. Choose the lower value of the two equations. Switching frequencies higher than these values result in pulse skipping or the lack of overcurrent protection during a short circuit.

The typical minimum on-time, t_on(min), is 130 ns for the TPS5401. For this example, the output voltage is 5 V and the maximum input voltage is 35 V, which allows for a maximum switch frequency up to 1213 kHz when including the inductor resistance, on-resistance, and diode voltage in Equation 10. To ensure overcurrent runaway is not a concern during short circuits in your design, use Equation 11 or the solid curve in Figure 37 to determine the maximum switching frequency. With a maximum input voltage of 35 V, assuming a diode voltage of 0.5 V, inductor resistance of 130 mΩ, switch resistance of 400 mΩ, a current-limit value of 0.94 A, and a short-circuit output voltage of 0.1 V, the maximum switching frequency is approximately 1265 kHz. Choosing high frequency can reduce external component size but results in higher switching loss. To achieve a balanced design, a switching frequency of 700 kHz is used. To determine the timing resistance for a given switching frequency, use Equation 9 to get a nearest standard resistance of 165 kΩ. The switching frequency is set to 698 kHz by the resistor R3 shown in Figure 40.

8.2.2.2 Output Voltage Setpoint

The output voltage of the TPS5401 is externally adjustable using a resistor divider network. In the application circuit of Figure 40, this divider network is comprised of R6 and R7. The relationship of the output voltage to the resistor divider is given by Equation 12:

Equation 12.

Choosing R7 = 10 kΩ, R6 is calculated to be 52.3 kΩ for an output voltage of 5 V.

Due to current leakage of the VSENSE pin, the current flowing through the feedback network should be greater than 1 μA in order to maintain the output voltage accuracy. This requirement makes the maximum value of R7 equal to 800 kΩ. Choosing higher resistor values decreases quiescent current and improve efficiency at low output currents but may introduce noise immunity problems.

8.2.2.3 Input Capacitor

The TPS5401 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor with at least 3 μF of effective capacitance, and in some applications additional bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple-current rating greater than the maximum input-current ripple of the TPS5401. Use Equation 13 to calculate the input voltage ripple.

The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor decreases as the dc bias across a capacitor increases.

For this example design, a ceramic capacitor with at least a 60-V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V, and 100 V, so a 100-V capacitor should be selected. For this example, two 2.2-μF, 100-V capacitors in parallel have been selected. Table 3 shows a selection of high-voltage capacitors. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 14.

Using the design example values, I_OUT(max) = 0.5 A, C_IN = 4.4 μF,and f_SW = 700 kHz, yields an input voltage ripple of 40.6 mV and a maximum rms input ripple current of 0.25 A when V_IN is equal to 10 V, which is 2 times the output voltage of 5 V.

Equation 13.

Equation 14.

8.2.2.4 Output Inductor Selection

To calculate the minimum value of the output inductor, use Equation 15.

Equation 15.

K_IND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.

The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor, because the output capacitor must have a ripple-current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer. However, the following guidelines may be used.

For designs using low-ESR output capacitors such as ceramics, a value as high as K_IND = 0.4 may be used. When using higher-ESR output capacitors, K_IND = 0.2 yields better results. Because the inductor ripple current is part of the PWM control system, the TPS5401 requires ripple current that is always greater than 30 mA for dependable operation. In a wide-input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. The maximum value of the input inductance is limited by Equation 16.

Equation 16.

For this design example, use K_IND = 0.3, and the minimum inductor value is calculated to be 42 μH. The nearest standard value was chosen: 47 μH. For the output-filter inductor, it is important that the root-mean-square (rms) current and saturation current ratings not be exceeded. The rms and peak inductor current can be found from Equation 17 to Equation 19.

Equation 17.

Equation 18.

Equation 19.

As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but require a larger value of inductance. Selecting higher ripple currents increases the output voltage ripple of the regulator but allows for a lower inductance value. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. For this design, I_LRIPPLE = 0.1303 A, I_L(RMS) = 0.501 A and I_L(peak) = 0.565 A. The inductor used is a Coilcraft MSS1048-473ML type, with a saturation current rating of 1.44 A and an rms current rating of 1.83 A.

8.2.2.5 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance must be selected based on the most stringent of these three criteria.

The desired response to a large change in the load current is the first criterion. The output capacitor must supply the load with current when the regulator cannot. This situation occurs if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also is temporarily unable to supply sufficient output current if there is a large, fast increase in the current needs of the load, such as when transitioning from no load to a full load. The regulator usually requires two or more clock cycles for the control loop to detect the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a tolerable amount of drop in the output voltage. Equation 20 shows the minimum output capacitance necessary to accomplish this.

Equation 20.

where

• ΔI_OUT is the change in output current
• f_SW is the regulator switching frequency
• ΔV_OUT is the allowable change in the output voltage
• R_ESR is the Equivalent Series Resistance (ESR) of the output capacitor

Equation 20 indicates the ESR must be less than ΔV_OUT/ΔI_OUT. For this example, the transient load response is specified as a 4% change in V_OUT for a load step from 0 A (no load) to 0.5 A (full load). In addition, ΔI_OUT = 0.5A and ΔV_OUT = 0.04 × 5 V = 0.2 V. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into account. Using these numbers gives a minimum capacitance of 7.14 μF for ceramic capacitor and 20.4 µF for electrolytic capacitor with 260 mΩ ESR.

The catch diode of the regulator cannot sink current, so any stored energy in the inductor produces an output voltage overshoot when the load current rapidly decreases. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor increases the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 21 is used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value, where L_OUT is the value of the inductor, I_OH is the output current under heavy load, I_OL is the output under light load, V_FIN is the final peak output voltage, and V_INI is the initial capacitor voltage. For this example, the worst-case load step is from 0.5 A to 0 A. The output voltage increases during this load transition, and the stated maximum in our specification is 4% of the output voltage. This makes V_FIN = 1.04 × 5 V = 5.2 V. V_INI is the initial capacitor voltage, which is the nominal output voltage of 5 V. Using these numbers in Equation 21 yields a minimum capacitance of 5.76 μF.

Equation 21.

Equation 22 calculates the minimum output capacitance needed to meet the output-voltage ripple specification, where f_SW is the switching frequency, V_ORIPPLE is the maximum allowable output voltage ripple, and I_LRIPPLE is the inductor ripple current. Equation 22 shows the ESR of the output capacitor must be less than V_ORIPPLE/I_LRIPPLE to meet the output-voltage ripple requirement. Low-ESR capacitors are preferred to keep the output-voltage ripple low. If a high-ESR electrolytic capacitor is used, a small ESR ceramic capacitor is recommended to be in parallel with the electrolytic capacitor to minimize the output voltage ripple. In this application, an aluminum electrolytic capacitor is chosen as the output capacitor. It has 260 mΩ ESR. Equation 22 yields 1.44 µF.

Equation 22.

The most stringent criterion for the output capacitor is 20.5 µF of capacitance to keep the output voltage in regulation during a load transient in this example.

Additional capacitance de-ratings for aging, temperature and dc bias should be factored in, which increases this minimum value. For this example, a 220 µF electrolytic capacitor with 260 mΩ of ESR can be used for low cost target.

Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the root-mean-square (rms) value of the maximum ripple current. Equation 23 can be used to calculate the rms ripple current the output capacitor must support. For this application, Equation 23 yields 37.6 mA.

Equation 23.

8.2.2.6 Catch Diode

The TPS5401 requires an external catch diode between the PH pin and GND. The selected diode must have a reverse voltage rating equal to or greater than V_IN(MAX). The peak current rating of the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes are typically a good choice for the catch diode, due to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.

Typically, when the voltage and current ratings for the diode are higher, then the forward voltage is higher. Because the design example has an input voltage up to 42 V, a diode with a minimum of 42-V reverse voltage is selected.

For the example design, the B160A Schottky diode is selected for its lower forward voltage, and it comes in a larger package size which has good thermal characteristics over small devices. The typical forward voltage of the B160A is 0.5 V.

The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode, which equals the conduction losses of the diode. At higher switch frequencies, the ac losses of the diode must be taken into account. The ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery. Equation 24 is used to calculate the total power dissipation, conduction losses plus ac losses, of the diode.

The B160A has a junction capacitance (C_J) of 110 pF. Using Equation 24, the selected diode dissipates 0.29 W. This power dissipation, depending on mounting techniques, should produce a 5.9°C temperature rise in the diode when the input voltage is 42 V and the load current is 0.5 A.

If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode which has a low leakage current and slightly higher forward voltage drop.

Equation 24.

8.2.2.7 Slow-Start Capacitor

The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage-slew rate. This is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS5401 reach the current limit, whereas excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage-slew rate solves both of these problems.

The slow-start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 25 can be used to find the minimum slow-start time, t_SS, necessary to charge the output capacitor, C_OUT, from 10% to 90% of the output voltage, V_OUT, with an average slow-start current of I_SSAVG. In the example, to charge the 220 μF output capacitor up to 5 V while only allowing the average input current I_SSAVG to be 0.2 A would require a 4.4-ms slow-start time.

Equation 25.

When the slow-start time is known, the slow-start capacitor value can be calculated using Equation 4. For the example circuit, the slow-start time is set to a value of 3.2 ms, which requires a 0.01-µF capacitor.

8.2.2.8 Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or higher voltage rating.

8.2.2.9 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS5401. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brownouts when the input voltage is falling. The supply should turn on and start switching once the input voltage increases above power-up threshold (enabled). After the regulator starts switching, it should continue to do so until the input voltage falls below the power-down threshold (UVLO stop).

The programmable UVLO and enable voltages are set using a resistor divider between V_IN and ground to the EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example application, because the minimum input voltage is 7.5 V, when the maximum input voltage is 35 V, the voltage at the EN pin exceeds the absolute voltage rating of the EN pin. So the UVLO is not set externally in this design.

8.2.2.10 Compensation

The external compensation used with the TPS5401 allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric is supported. This design example uses an aluminum electrolytic output capacitor. A design example with the ceramic dielectric output capacitors can be found in the TPS54040 data sheet (SLVS918). More accurate designs can be found in the WEBENCH software.

The peak-current mode PWM modulator and the output filter generate a pair of power stage pole and zero which are determined using Equation 26 and Equation 27.

Equation 26.

Equation 27.

A type 2A compensation scheme is recommended for the TPS5401. As R_C, C_C, C_P shown in Figure 41, the compensation components are chosen to set the desired loop crossover frequency and phase margin for output filter components. The type 2A compensation has the following characteristics: a dc gain, a low-frequency pole, and a mid-frequency zero / pole pair.

Figure 41. The Compensation Recommended for the TPS5401

The dc gain is determined by Equation 28:

Equation 28.

where

• A_DCEA is the error amplifier open-loop dc gain. It is 10,000 V/V.

The low-frequency pole is determined by Equation 29:

Equation 29.

where

• R_O is the output resistance of the error amplifier. It can be calculated by Equation 30.

Equation 30.

The mid-frequency zero is determined by Equation 31.

Equation 31.

Additionally, the mid-frequency pole is given by Equation 32.

Equation 32.

The first step is to choose the closed-loop crossover frequency f_CO. In general, the closed-loop crossover frequency could be less than 1/10 of the minimum operating frequency. For the TPS5401, the maximum closed-loop crossover frequency must not be not greater than 40 kHz. For this example, we choose 15-kHz crossover frequency. Next, by definition, the magnitude of the loop gain at the crossover frequency is 0 dB. By placing the compensation zero at the power stage pole, and the mid-compensation pole at the power stage zero, the R_C, C_C and C_P can be approximately calculated by Equation 33 through Equation 35.

Equation 33.

Equation 34.

Equation 35.

where

• gm_PS is the power-stage transconductance. It is 1.9 A/V
• gm_EA is the error-amplifier transconductance. It is 97 μA/V

For this design, the calculated values are as follows:

• R3 = 37.4 kΩ
• C6 = 2200 pF
• C7 = 22 pF

8.2.2.11 Discontinuous Mode and Eco-mode Control-Scheme Boundary

With an input voltage of 34 V, the power supply enters discontinuous mode when the output current is less than 50 mA. The power supply enters Eco-mode control scheme when the output current is lower than 30 mA.

8.2.2.12 Power Dissipation Estimate

The following formulas show how to estimate the IC power dissipation under continuous-conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous-conduction mode (DCM).

The power dissipation of the IC includes conduction loss (P_CON), switching loss (P_sw), gate-drive loss (P_GD), and supply current (P_SUP).

Equation 36.

Equation 37.

Equation 38.

Equation 39.

Therefore, total power dissipation is:

Equation 40.

For a given ambient temperature T_A, the junction temperature T_J can be estimated by Equation 41.

Equation 41.

where

• R_θJA is the thermal resistance of the package (°C/W)

For given T_J(max) = 150°C, the maximum allowed ambient temperature can be estimated by Equation 42.

Equation 42.

There are additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and trace resistance that impact the overall efficiency of the regulator.