ZHCSCL8 July 2014 TPS54060-EP
PRODUCTION DATA.
- 1 特性
- 2 应用范围
- 3 说明
- 4 简化电路原理图
- 5 修订历史记录
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Fixed Frequency PWM Control
- 8.3.2 Slope Compensation Output Current
- 8.3.3 Low-Dropout Operation and Bootstrap Voltage (Boot)
- 8.3.4 Error Amplifier
- 8.3.5 Voltage Reference
- 8.3.6 Adjusting the Output Voltage
- 8.3.7 Enable and Adjusting UVLO
- 8.3.8 Slow Start/Tracking Pin (SS/TR)
- 8.3.9 Overload Recovery Circuit
- 8.3.10 Sequencing
- 8.3.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 8.3.12 Overcurrent Protection and Frequency Shift
- 8.3.13 Selecting the Switching Frequency
- 8.3.14 How to Interface to RT/CLK Pin
- 8.3.15 Power Good (PWRGD Pin)
- 8.3.16 Overvoltage Transient Protection (OVTP)
- 8.3.17 Thermal Shutdown
- 8.3.18 Small Signal Model for Loop Response
- 8.3.19 Simple Small Signal Model for Peak Current Mode Control
- 8.3.20 Small Signal Model for Frequency Compensation
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Selecting the Switching Frequency
- 9.2.2.2 Output Inductor Selection (LO)
- 9.2.2.3 Output Capacitor
- 9.2.2.4 Catch Diode
- 9.2.2.5 Input Capacitor
- 9.2.2.6 Slow Start Capacitor
- 9.2.2.7 Bootstrap Capacitor Selection
- 9.2.2.8 UVLO Set Point
- 9.2.2.9 Output Voltage and Feedback Resistors Selection
- 9.2.2.10 Compensation
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械封装和可订购信息
6 Pin Configuration and Functions
DGQ Package
10 Pins
(Top View)
Pin Functions
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| BOOT | 1 | O | A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. | |
| COMP | 8 | O | Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. | |
| EN | 3 | I | Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout (UVLO) with two resistors. | |
| GND | 9 | — | Ground | |
| PH | 10 | I | The source of the internal high-side power MOSFET. | |
| PowerPAD | 11 | — | GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. | |
| PWRGD | 6 | O | An open-drain output, asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or EN shut down. | |
| RT/CLK | 5 | I | Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set function. | |
| SS/TR | 4 | I | Slow-start and tracking. An external capacitor connected to this pin sets the output rise time. Because the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. | |
| VIN | 2 | I | Input supply voltage, 3.5 to 60 V. | |
| VSENSE | 7 | I | Inverting node of the transconductance (gM) error amplifier. | |