ZHCSCL8 July   2014 TPS54060-EP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation Output Current
      3. 8.3.3  Low-Dropout Operation and Bootstrap Voltage (Boot)
      4. 8.3.4  Error Amplifier
      5. 8.3.5  Voltage Reference
      6. 8.3.6  Adjusting the Output Voltage
      7. 8.3.7  Enable and Adjusting UVLO
      8. 8.3.8  Slow Start/Tracking Pin (SS/TR)
      9. 8.3.9  Overload Recovery Circuit
      10. 8.3.10 Sequencing
      11. 8.3.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      12. 8.3.12 Overcurrent Protection and Frequency Shift
      13. 8.3.13 Selecting the Switching Frequency
      14. 8.3.14 How to Interface to RT/CLK Pin
      15. 8.3.15 Power Good (PWRGD Pin)
      16. 8.3.16 Overvoltage Transient Protection (OVTP)
      17. 8.3.17 Thermal Shutdown
      18. 8.3.18 Small Signal Model for Loop Response
      19. 8.3.19 Simple Small Signal Model for Peak Current Mode Control
      20. 8.3.20 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Skip Eco-Mode
      2. 8.4.2 DCM and Eco-Mode Boundary
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Selecting the Switching Frequency
        2. 9.2.2.2  Output Inductor Selection (LO)
        3. 9.2.2.3  Output Capacitor
        4. 9.2.2.4  Catch Diode
        5. 9.2.2.5  Input Capacitor
        6. 9.2.2.6  Slow Start Capacitor
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  UVLO Set Point
        9. 9.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 9.2.2.10 Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Dissipation Estimate
    2. 10.2 Power Supply Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Estimated Circuit Area
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 术语表
  13. 13机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage VIN –0.3 65 V
EN –0.3 5
BOOT 75
VSENSE –0.3 3
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 3.6
Output voltage BOOT-PH 8 V
PH –0.6 65
PH, 10-ns transient –2 65
Voltage difference PAD to GND –200 200 mV
Source current EN 100 μA
BOOT 100 mA
VSENSE 10 μA
PH Current limit A
RT/CLK 100 μA
Sink current VIN Current limit A
COMP 100 μA
PWRGD 10 mA
SS/TR 200 μA
Operating junction temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –1000 1000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –500 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
TA Ambient temperature –55 125 °C
TJ Junction temperature –55 150 °C
V(VIN) 3.5 60 V

7.4 Thermal Information

THERMAL METRIC(1)(2) TPS54060 UNIT
DGQ (10 PINS)
RθJA Junction-to-ambient thermal resistance (standard board) 62.5 °C/W
Junction-to-ambient thermal resistance (custom board)(3) 57
RθJC(top) Junction-to-case (top) thermal resistance 83
RθJB Junction-to-board thermal resistance 28
ψJT Junction-to-top characterization parameter 1.7
ψJB Junction-to-board characterization parameter 20.1
RθJC(bot) Junction-to-case (bottom) thermal resistance 21
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
(3) Test boards conditions:
  1. 3 inches × 3 inches, 2 layers, thickness: 0.062 inch
  2. 2-oz. copper traces located on the top of the PCB
  3. 2-oz. copper ground plane, bottom layer
  4. 6 thermal vias (13 mil) located under the device package

7.5 Electrical Characteristics

TJ = –55°C to 150°C, VIN = 3.5 to 60 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 3.5 60 V
Internal UVLO threshold No voltage hysteresis, rising and falling 2.5 V
Shutdown supply current V(EN) = 0 V, 3.5 V ≤ V(VIN) ≤ 60 V 1.3 8 μA
Operating: nonswitching supply current V(VSENSE) = 0.83 V, V(VIN) = 12 V 116 150
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling 0.9 1.25 1.6 V
Input current Enable threshold 50 mV –3.8 μA
Enable threshold –50 mV –0.9
Hysteresis current –2.9 μA
VOLTAGE REFERENCE
Voltage reference TJ = 25°C 0.792 0.8 0.808 V
0.78 0.8 0.821
HIGH-SIDE MOSFET
On-resistance V(VIN) = 3.5 V, BOOT-PH = 3 V 300 mΩ
V(VIN) = 12 V, BOOT-PH = 6 V 200 465
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 97 μMhos
Error amplifier transconductance (gM) during slow start –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
V(VSENSE) = 0.4 V		 26 μMhos
Error amplifier dc gain V(VSENSE) = 0.8 V 10000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±7 μA
COMP to switch current transconductance 1.9 A/V
CURRENT LIMIT
Current limit threshold V(VIN) = 12 V 0.5 0.94 A
THERMAL SHUTDOWN
Thermal shutdown 182 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode V(VIN) = 12 V 130 2500 kHz
ƒSW Switching frequency V(VIN) = 12 V, RT = 200 kΩ 440 581 740 kHz
Switching frequency range using CLK mode V(VIN) = 12 V 300 2200 kHz
Minimum CLK input pulse width 40 ns
RT/CLK high threshold V(VIN) = 12 V 1.9 2.2 V
RT/CLK low threshold V(VIN) = 12 V 0.5 0.7 V
RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series 60 ns
PLL lock in time Measured at 500 kHz 100 μs
SLOW START AND TRACKING (SS/TR)
Charge current V(SS/TR) = 0.4 V 2 μA
SS/TR-to-VSENSE matching V(SS/TR) = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1.0 V
SS/TR discharge current (overload) V(VSENSE) = 0 V, V(SS/TR) = 0.4 V 112 μA
SS/TR discharge voltage V(VSENSE) = 0 V 54 mV
POWER GOOD (PWRGD PIN)
V(VSENSE) VSENSE threshold VSENSE falling (fault) 92%
VSENSE rising (good) 94%
VSENSE rising (fault) 109%
VSENSE falling (good) 107%
Hysteresis VSENSE falling 2%
Output high leakage V(VSENSE) = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On resistance I(PWRGD) = 3 mA, V(VSENSE) < 0.79 V 50 Ω
Minimum VIN for defined output V(PWRGD) < 0.5 V, I(PWRGD) = 100 μA 0.95 1.5 V

7.6 Typical Characteristics

C001_SLVSCF8.png
VIN = 12 V
Figure 1. On Resistance vs Junction Temperature
C003_SLVSCF8.png
VIN = 12 V
Figure 3. Switch Current Limit vs Junction Temperature
C005_SLVS919.gif
VIN = 12 V TJ = 25°C
Figure 5. Switching Frequency vs RT/CLK Resistance High Frequency Range
C005_SLVSCF8.png
VIN = 12 V
Figure 7. EA Transconductance During Slow Start vs Junction Temperature
C007_SLVSCF8.png
VIN = 12 V
Figure 9. EN Pin Voltage vs Junction Temperature
C009_SLVSCF8.png
VIN = 12 V V(EN) = Threshold –50 mV
Figure 11. EN Pin Current vs Junction Temperature
C011_SLVSCF8.png
VIN = 12 V
Figure 13. SS/TR Discharge Current vs Junction Temperature
C012_SLVSCF8.png
VIN = 12 V
Figure 15. Shutdown Supply Current vs Junction Temperature
C013_SLVSCF8.png
VIN = 12 V V(VSENSE) = 0.83 V
Figure 17. VIN Supply Current vs Junction Temperature
C014_SLVSCF8.png
VIN = 12 V
Figure 19. PWRGD On Resistance vs Junction Temperature
C016_SLVSCF8.png
Figure 21. Boot-PH UVLO vs Junction Temperature
C023_SLVS919.gif
VIN = 12 V TJ = 25°C
Figure 23. SS/TR To Vsense Offset vs VSENSE
C002_SLVSCF8.png
VIN = 12 V
Figure 2. Voltage Reference vs Junction Temperature
C004_SLVSCF8.png
VIN = 12 V RT = 200 kΩ
Figure 4. Switching Frequency vs Junction Temperature
C006_SLVS919.gif
VIN = 12 V TJ = 25°C
Figure 6. Switching Frequency vs RT/CLK Resistance Low Frequency Range
C006_SLVSCF8.png
VIN = 12 V
Figure 8. EA Transconductance vs Junction Temperature
C008_SLVSCF8.png
VIN = 12 V V(EN) = Threshold 50 mV
Figure 10. EN Pin Current vs Junction Temperature
C010_SLVSCF8.png
VIN = 12 V
Figure 12. SS/TR Charge Current vs Junction Temperature
C014_SLVS919.gif
VIN = 12 V TJ = 25°C
Figure 14. Switching Frequency vs VSENSE
C016_SLVS919.gif
TJ = 25°C
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
C018_SLVS919.gif
TJ = 25°C V(VSENSE) = 0.83 V
Figure 18. VIN Supply Current vs Input Voltage
C015_SLVSCF8.png
VIN = 12 V
Figure 20. PWRGD Threshold vs Junction Temperature
C017_SLVSCF8.png
Figure 22. Input Voltage (UVLO) vs Junction Temperature
C018_SLVSCF8.png
VIN = 12 mV V(SS/TR) = 0.2 V
Figure 24. SS/TR To VSENSE Offset vs Temperature
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