SLVS919C January 2009 – September 2015 TPS54060
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | VIN | –0.3 | 65 | V |
EN | –0.3 | 5 | ||
VSENSE | –0.3 | 3 | ||
COMP | –0.3 | 3 | ||
PWRGD | –0.3 | 6 | ||
SS/TR | –0.3 | 3 | ||
RT/CLK | –0.3 | 3.6 | ||
BOOT-PH | –0.3 | 8 | ||
PH | –0.6 | 65 | ||
PH, 10-ns Transient | –2 | 65 | ||
Voltage Difference | Thermal PAD to GND | ±200 | mV | |
Source current | EN | 100 | μA | |
BOOT | 100 | mA | ||
VSENSE | 10 | μA | ||
PH | Current Limit | A | ||
RT/CLK | 100 | μA | ||
Sink current | VIN | Current Limit | A | |
COMP | 100 | μA | ||
PWRGD | 10 | mA | ||
SS/TR | 200 | μA | ||
Operating junction temperature | –40 | 150 | °C | |
Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply input voltage, VVIN | 3.5 | 60 | V | |
Output voltage, VO | 0.8 | 57 | V | |
Output current, IO | 0 | 0.5 | A | |
Operating junction temperature, TJ | -40 | 150 | °C |
THERMAL METRIC(1)(2)(2) | TPS54060 | UNIT | ||
---|---|---|---|---|
DGQ (VSSOP) | DRC (VSON) | |||
10 PINS | 10 PINS | |||
RθJA | Junction-to-ambient thermal resistance (standard board) | 62.5 | 40 | °C/W |
RθJA | Junction-to-ambient thermal resistance (custom board) (3) | 57 | 56.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.7 | 0.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 20.1 | 7.5 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 83 | 65 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | 21 | 7.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 28 | 8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY VOLTAGE (VIN PIN) | |||||||
Operating input voltage | 3.5 | 60 | V | ||||
Internal undervoltage lockout threshold | No voltage hysteresis, rising and falling | 2.5 | V | ||||
Shutdown supply current | EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V | 1.3 | 4 | μA | |||
Operating : nonswitching supply current | VSENSE = 0.83 V, VIN = 12 V, 25°C | 116 | 136 | ||||
ENABLE AND UVLO (EN PIN) | |||||||
Enable threshold voltage | No voltage hysteresis, rising and falling, 25°C | 0.9 | 1.25 | 1.55 | V | ||
Input current | Enable threshold +50 mV | –3.8 | μA | ||||
Enable threshold –50 mV | –0.9 | ||||||
Hysteresis current | –2.9 | μA | |||||
VOLTAGE REFERENCE | |||||||
Voltage reference | TJ = 25°C | 0.792 | 0.8 | 0.808 | V | ||
0.784 | 0.8 | 0.816 | |||||
HIGH-SIDE MOSFET | |||||||
On-resistance | VIN = 3.5 V, BOOT-PH = 3 V | 300 | mΩ | ||||
VIN = 12 V, BOOT-PH = 6 V | 200 | 410 | |||||
ERROR AMPLIFIER | |||||||
Input current | 50 | nA | |||||
Error amplifier transconductance (gM) | –2 μA < ICOMP < 2 μA, VCOMP = 1 V | 97 | μS | ||||
Error amplifier transconductance (gM) during slow start | –2 μA < ICOMP < 2 μA, VCOMP = 1 V, VVSENSE = 0.4 V |
26 | μS | ||||
Error amplifier dc gain | VVSENSE = 0.8 V | 10,000 | V/V | ||||
Error amplifier bandwidth | 2700 | kHz | |||||
Error amplifier source/sink | V(COMP) = 1 V, 100 mV overdrive | ±7 | μA | ||||
COMP to switch current transconductance | 1.9 | A/V | |||||
CURRENT LIMIT | |||||||
Current limit threshold | VIN = 12 V, TJ = 25°C | 0.6 | 0.94 | A | |||
THERMAL SHUTDOWN | |||||||
Thermal shutdown | 182 | °C | |||||
SLOW START AND TRACKING (SS/TR) | |||||||
Charge current | VSS/TR = 0.4 V | 2 | μA | ||||
SS/TR-to-VSENSE matching | VSS/TR = 0.4 V | 45 | mV | ||||
SS/TR-to-reference crossover | 98% nominal | 1.0 | V | ||||
SS/TR discharge current (overload) | VSENSE = 0 V, V(SS/TR) = 0.4 V | 112 | μA | ||||
SS/TR discharge voltage | VSENSE = 0 V | 54 | mV | ||||
POWER GOOD (PWRGD PIN) | |||||||
VVSENSE | VSENSE threshold | VSENSE falling | 92% | ||||
VSENSE rising | 94% | ||||||
VSENSE rising | 109% | ||||||
VSENSE falling | 107% | ||||||
Hysteresis | VSENSE falling | 2% | |||||
Output high leakage | VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C | 10 | nA | ||||
On resistance | I(PWRGD) = 3 mA, VSENSE < 0.79 V | 50 | Ω | ||||
Minimum VIN for defined output | V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA | 0.95 | 1.5 | V |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
Minimum CLK input pulse width | 40 | ns | |||
RT/CLK falling edge to PH rising edge delay | 60 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fSW | Switching frequency | RT = 200 kΩ | 450 | 581 | 720 | kHz |
Switching Frequency Range using RT mode | 100 | 2500 | kHz | |||
Switching frequency range using CLK mode | 300 | 2200 | kHz | |||
PLL lock in time | Measured at 500 kHz | 100 | μs |