10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. Guidelines are as follows. See Figure 64 for a PCB layout example.

• The input bypass capacitor for PVIN to PGND should be placed as close as possible to the TPS54116-Q1 with short and wide connections to minimize parasitic inductance.
• The input bypass capacitor for AVIN should be placed as close as possible to the TPS54116-Q1 with a short return to the AGND pin. This capacitor and pin should also be tied to the input voltage before the PVIN bypass capacitors to limit the switching noise from PVIN.
• The output capacitor for VTT to VTTGND should be placed as close as possible to the TPS54116-Q1 with short and wide connections to minimize parasitic inductance and resistance. Too much parasitic inductance and resistance can affect the stability of the high performance VTT LDO.
• The VTTSNS pin should be connected tothe VTT output capacitors as a seperate trace from the high current VTT power trace. If sensing the voltage at the pont of the load is required, it is recommended to also attach the output capacitors at that point while still minimizing parasitic inductance and resistance.
• The input bypass capacitor for LDOIN to VTTGND should be placed as close as possible to the TPS54116-Q1 with short and wide connections to minimize parasitic inductance. This capacitor is used to supply the transient current to the VTT output.
• The VDDQSNS pin should be routed as a separate trace from the high current VDDQ trace and connect near the point of regulation for VDDQ.
• The top of the FB resistor divider should be routed as a separate trace from the high current VDDQ trace and connect near the the point of regulation for VDDQ.
• The analog control circuits should have a return path to the quiet AGND and not overlap with the noisey PGND. Sensitive pins containing analog control circuits are RT/SYNC, SS/TRK, COMP, FB, ILIM, and VTTREF. It is important to minimize the length of the traces connected to the RT/SYNC, COMP, FB and ILIM pins.
• The PGND pins, AGND and VTTGND pin should be tied directly to the power pad under the IC to provide a low impedance connection between the pins.
• The BOOT capacitor should connect directly between the BOOT and SW pins.
• The SW pin should be routed to the output inductor with a short and wide trace to minimize capacitive coupling.
• The thermal pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. For operation at full rated load, the top side ground area and bottom side ground area along with any additional internal ground planes must provide adequate heat dissipating area. For best thermal performance minimize cuts in the bottom side ground copper.
• Additional vias can be used to connect the top side ground area to the internal planes near the input and output capacitors for the buck converter and VTT LDO.

The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.

10.2 Layout Example

Figure 64. PCB Layout Example