ZHCSFG9A August   2016  – August 2016 TPS54116-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Bootstrap Voltage (BOOT) and Low Dropout Operation
      3. 7.3.3  Error Amplifier
      4. 7.3.4  Voltage Reference and Adjusting the Output Voltage
      5. 7.3.5  Enable and Adjusting Undervoltage Lockout
      6. 7.3.6  Soft Start and Tracking
      7. 7.3.7  Start-up into Pre-Biased Output
      8. 7.3.8  Power Good
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/SYNC)
      11. 7.3.11 Buck Overcurrent Protection
      12. 7.3.12 Overvoltage Transient Protection
      13. 7.3.13 VTT Sink and Source Regulator
      14. 7.3.14 VTTREF
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Inductor Selection
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Input Capacitor
        5. 8.2.2.5  Soft Start Capacitor
        6. 8.2.2.6  Undervoltage Lock Out Set Point
        7. 8.2.2.7  Bootstrap Capacitor
        8. 8.2.2.8  Power Good Pullup
        9. 8.2.2.9  ILIM Resistor
        10. 8.2.2.10 Output Voltage and Feedback Resistors Selection
        11. 8.2.2.11 Compensation
        12. 8.2.2.12 LDOIN Capacitor
        13. 8.2.2.13 VTTREF Capacitor
        14. 8.2.2.14 VTT Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RTW|24
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage Range PVIN, AVIN, ENSW, ENLDO, PGOOD -0.3 7 V
FB, COMP, SS/TRK, ILIM -0.3 3 V
RT/SYNC -0.3 6 V
BOOT with respect to SW -0.3 7 V
LDOIN, VTTSNS, VDDQSNS -0.3 3.6 V
SW -0.6 7 V
SW, 10-ns transient -4 10 V
VTT, VTTREF -0.3 3.6 V
Current Range RT/SYNC -100 100 µA
PGOOD -5 5 mA
Operating junction temperature -40 150 °C
Storage temperature, Tstg -65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V(AVIN), V(PVIN) Input voltage 2.95 6 V
VOUT Buck output voltage 0.6 4.5 V
IOUT Buck output current 0 4 A
V(VDDQSNS) VDDQSNS input voltage 1 3.5 V
V(LDOIN) LDOIN input voltage VTT + VDO 3.5 V
V(VTT), V(VTTREF) VTT and VTTREF output voltage 0.5 3.5 V

6.4 Thermal Information

THERMAL METRIC(1) TPS54116-Q1 UNIT
RTW (WQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 36.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 35.0
RθJB Junction-to-board thermal resistance 14.3
ψJT Junction-to-top characterization parameter 0.4
ψJB Junction-to-board characterization parameter 14.4
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TJ = -40°C to 150°C, AVIN = PVIN = 2.95 V to 6 V, VLDOIN = VDDQSNS (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (AVIN and PVIN PINS)
AVIN and PVIN operating 2.95 6 V
AVIN internal UVLO threshold AVIN rising 2.7 2.8 V
AVIN internal UVLO hysteresis 0.05 0.12 V
Iq shutdown V(ENSW) = V(ENLDO) = 0 V, V(VDDQSNS) = 1.8 V, TJ = 25°C 1 3.5 µA
Iq operating — LDO and buck enabled V(ENSW) = V(ENLDO) = V(AVIN) = 5 V, V(FB) = 0.7 V, V(VDDQSNS) = 1.8 V, TJ = 25°C 650 800 µA
Iq operating — LDO enabled, buck disabled V(ENLDO) = V(AVIN) = 5 V, V(ENSW) = 0 V, V(VDDQSNS) = 1.8 V, TJ = 25°C 190 300 µA
Iq operating — LDO disabled, buck enabled V(ENSW) = V(AVIN) = 5 V, V(ENLDO) = 0 V, V(FB) = 0.7 V, V(VDDQSNS) = 1.8 V, TJ = 25°C 570 700 µA
ENABLE (ENSW and ENLDO PINS)
VENRISING ENLDO rising threshold ENLDO voltage ramping up 1.20 V
VENFALLING ENLDO falling threshold ENLDO voltage ramping down 1.17
ENLDO input current above voltage threshold V(ENLDO) = Enable threshold + 50 mV -4.4 µA
Ip ENLDO input current below voltage threshold V(ENLDO) = Enable threshold - 50 mV -1.7
Ih ENLDO hysteresis current -2.7
VENRISING ENSW rising threshold ENSW voltage ramping up 1.20 V
VENFALLING ENSW falling threshold ENSW voltage ramping down 1.17
ENSW input current above voltage threshold V(ENSW) = Enable threshold + 50 mV -4.4 µA
Ip ENSW input current below voltage threshold V(ENSW) = Enable threshold - 50 mV -1.7
Ih ENSW hysteresis current -2.7
Input current above voltage threshold with ENLDO and ENSW connected V(ENLDO) = V(ENSW) = Enable threshold + 50 mV -8.5 µA
Input current below voltage threshold with ENLDO and ENSW connected V(ENLDO) = V(ENSW) = Enable threshold - 50 mV -3.4 µA
Hysteresis current with ENLDO and ENSW connected -5.1 µA
VOLTAGE REFERENCE AND ERROR AMPLIFIER (FB AND COMP PINS)
VREF Voltage Reference 0.594 0.6 0.606 V
FB pin input current 7 nA
gmEA Error Amp transconductance (gm) -2 µA < I(COMP) < 2 µA, V(COMP) = 1 V 260 360 µS
Error Amp source/sink V(COMP) = 1 V, V(FB) = 100 mV overdrive 22 µA
MOSFETS AND POWER STAGE (SW AND BOOT PINS)
High side switch resistance V(BOOT-SW) = 5 V 33 66 mΩ
V(BOOT-SW) = 3.3 V 42 84
Low side switch resistance V(PVIN) = 5 V 25 50 mΩ
V(PVIN) = 3.3 V 30 60
BOOT-SW UVLO V(PVIN) = 2.95 V 2.2 V
High-side FET current limit V(PVIN) = 6V, R(ILIM) = 100k 5.2 6.6 8.2 A
High-side FET current limit V(PVIN) = 6V, R(ILIM) = 200k 1.5 3 3.8 A
Low-side FET reverse current limit 2 4.5 A
gmPS V(COMP) to I(SW)peak transconductance R(ILIM) = 100k 16 A/V
Minimum pulse width Measured at 50% points on V(SW), IOUT = 2 A 60 ns
Minimum pulse width Measured at 50% points V(SW), V(PVIN) = 5 V, IOUT = 0 A, TJ = -40°C to 125°C 100 125 ns
Minimum off-time Prior to skipping off pulses, IOUT = 2 A 60 ns
TIMING RESISTOR AND EXTERNAL CLOCK (RT/SYNC PIN)
Switching frequency range using RT mode 100 2500 kHz
Switching frequency R(RT/SYNC) = 150 kΩ 370 400 430 kHz
R(RT/SYNC) = 27 kΩ 1910 2070 2230 kHz
V(RT/SYNC) > 2.2 V or V(RT/SYNC) < 0.35 V 340 420 480 kHz
Switching frequency range using SYNC mode 100 2500 kHz
Minimum SYNC input pulse width 10 ns
RT/SYNC high threshold 1.5 2.2 V
RT/SYNC low threshold 0.35 0.4 V
RT/SYNC rising edge to SW rising edge delay fSW = 500 kHz 30 45 80 ns
RT to SYNC lock in time R(RT/SYNC) = 150 kΩ 55 µs
SYNC to RT lock in time 60 µs
Internal RT to SYNC lock in time Logic high or logic low at RT/SYNC to SYNC signal 55 µs
SYNC to internal RT lock in time SYNC signal to logic high or logic low at RT/SYNC 60 µs
SOFT START AND TRACKING (SS/TRK PIN)
VSSTHR SS voltage threshold 0.15 V
ISS Charge Current V(SS/TRK) < VSSTHR 47 µA
V(SS/TRK) > VSSTHR 1.5 2.4 3.2 µA
SS/TRK to FB matching V(SS/TRK) = 0.3 V 60 mV
SS/TRK to reference crossover 98% normal 0.85 1 V
SS/TRK discharge voltage (overload) V(FB) = 0 V 120 mV
SS/TRK discharge voltage (fault) V(FB) = 0 V 5 mV
SS/TRK discharge current (overload) V(FB) = 0 V, V(SS/TRK) = 0.4 V 160 µA
SS/TRK discharge current (AVIN UVLO, ENSW low, thermal fault) V(AVIN) = 5 V, V(SS/TRK) = 0.4 V 760 µA
POWER GOOD (PGOOD PIN)
Threshold V(FB) falling (fault) 91 95 % VREF
V(FB) rising (good) 94
V(FB) rising (fault) 105 109
V(FB) falling (good) 106
Hysteresis V(FB) falling and rising 3
Output high leakage V(FB) = VREF, V(PGOOD) = 5.5 V 5 125 nA
On resistance V(AVIN) = 2.95 V 85 170 Ω
Minimum V(AVIN) for valid output V(PGOOD) < 0.5 V, I(PGOOD) = 100 µA 1.3 1.7 V
TERMINATION REGULATOR INPUTS (VLDOIN AND VDDQSNS PINS)
V(LDOIN) Operating 3.5 V
VDO DC V(LDOIN) – V(VTT) dropout 1.2 V < V(VDDQSNS) < 2.5 V, I(VTT) = 0.5 A, V(VTT) = V(VTTREF) - 40 mV 0.15 V
VDO DC V(LDOIN) – V(VTT) dropout 1.2 V < V(VDDQSNS) < 2.5 V, I(VTT) = 1.5 A, V(VTT) = V(VTTREF) - 40 mV 0.45 V
VLDOIN supply current V(LDOIN) = 1.8 V, TJ = 25°C 1 µA
VDDQSNS input current V(VDDQSNS) = 1.8 V 39 46 µA
VTTREF OUTPUT (VTTREF PIN)
V(VTTREF) VTTREF output voltage V(VDDQSNS)/2 V
V(VTTREF)TOL VTTREF output voltage difference from V(VDDQSNS)/2 |I(VTTREF)| < 10 mA, V(VDDQSNS) = 1.8 V -18 18 mV
|I(VTTREF)| < 10 mA, V(VDDQSNS) = 1.5 V -15 15
|I(VTTREF)| < 10 mA, V(VDDQSNS) = 1.2 V -15 15
|I(VTTREF)| < 5 mA, V(VDDQSNS) = 1.2 V -12 12
I(VTTREF)SRC VTTREF source current limit V(VDDQSNS) = 1.8 V, V(VTTREF) = 0 V 10 18 mA
I(VTTREF)SNK VTTREF sink current limit V(VDDQSNS) = 0 V, V(VTTREF) = 1.8 V 10 19 mA
I(VTTREF)DIS VTTREF discharge current TJ = 25°C, V(VTTREF) = 0.5V, V(ENLDO) = 0 V 0.9 1.1 mA
VTT OUTPUT (VTT PIN)
V(VTT) VTT output voltage V(VTTREF) V
V(VTT)TOL VTT output voltage tolerance to VTTREF |I(VTT)|≤ 10 mA, 1.2 V ≤ V(VDDQSNS) ≤ 1.8 V -20 20 mV
|I(VTT)|≤ 1 A, 1.2 V ≤ V(VDDQSNS) ≤ 1.8 V -30 30
|I(VTT)|≤ 1.5 A, 1.2 V ≤ V(VDDQSNS) ≤ 1.8 V -40 40
I(VTT)SRC VTT source current limit V(VDDQSNS) = 1.8 V, V(VTT) = V(VTTSNS) = 0.7 V 1.5 2.5 A
I(VTT)SNK VTT sink current limit V(VDDQSNS) = 1.8 V, V(VTT) = V(VTTSNS) = 1.1 V 1.5 2.5 A
I(VTTSNS)BIAS VTTSNS input bias current -0.1 0.1 µA
I(VTT)DIS VTT discharge current TJ = 25°C, V(VTT) = 0.5 V, V(ENLDO) = 0 V 4.8 6 mA
THERMAL SHUTDOWN
Thermal shutdown temperature 175 ℃
Thermal shutdown hysteresis 16 ℃

6.6 Typical Characteristics

TPS54116-Q1 D001_SLVSCO3.gif
Figure 1. Shutdown Supply Current vs Temperature
TPS54116-Q1 D003_SLVSCO3.gif
Figure 3. Non-switching Supply Current - LDO Enabled and Buck Disabled vs Temperature
TPS54116-Q1 D005_SLVSCO3.gif
Figure 5. ENSW and ENLDO Voltage Threshold vs Temperature
TPS54116-Q1 D007_SLVSCO3.gif
Figure 7. ENSW and ENLDO Parallel Input Current vs Temperature
TPS54116-Q1 D009_SLVSCO3.gif
Figure 9. Error Amplifier Transconductance vs Temperature
TPS54116-Q1 D011_SLVSCO3.gif
V(PVIN) = 5 V
Figure 11. High-side Current Limit vs Temperature
TPS54116-Q1 D013_SLVSCO3.gif
Figure 13. V(COMP) to I(SW) Transconductance vs Temperature
TPS54116-Q1 D015_SLVSCO3.gif
TA = 25°C
Figure 15. Minimum pulse-width vs Load Current
TPS54116-Q1 D017_SLVSCO3.gif
TA = 25°C
Figure 17. Switching Frequency vs R(RT/SYNC) High Range
TPS54116-Q1 D019_SLVSCO3.gif
R(RT/SYNC) = 27 kΩ
Figure 19. Switching Frequency vs Temperature
TPS54116-Q1 D021_SLVSCO3.gif
V(SS/TRK) < VSS(THR)
Figure 21. I(SS/TRK) vs Temperature
TPS54116-Q1 D023_SLVSCO3.gif
TA = 25°C
Figure 23. V(FB) vs V(SS/TRK)
TPS54116-Q1 D026_SLVSCO3.gif
VDDQSNS = 1.8 V VIN = 5 V
Figure 25. VTTREF Regulation to VDDQSNS/2 vs I(VTTREF)
TPS54116-Q1 D028_SLVSCO3.gif
VDDQSNS = 1.35 V VIN = 5 V
Figure 27. VTTREF Regulation to VDDQSNS/2 vs I(VTTREF)
TPS54116-Q1 D030_SLVSCO3.gif
VDDQSNS = 1.8 V VIN = 5 V
Figure 29. VTT Regulation to VTTREF vs I(VTT)
TPS54116-Q1 D032_SLVSCO3.gif
VDDQSNS = 1.35 V VIN = 5 V
Figure 31. VTT Regulation to VTTREF vs I(VTT)
TPS54116-Q1 D034_SLVSCO3.gif
VDDQSNS = 1.5 V VIN = 5 V
Figure 33. VTT Dropout
TPS54116-Q1 D036_SLVSCO3.gif
V(VTT) = 1.5 V VIN = 5 V I(VTT) = –1 A
TA = 25°C
Figure 35. VTT Sinking Frequency Response
TPS54116-Q1 D045_SLVSCO3.gif
fSYNC = 2.1 MHz VIN = 5 V L = 744373240068
TA = 25°C
Figure 37. Efficiency
TPS54116-Q1 D047_SLVSCO3.gif
fSYNC = 400 kHz VIN = 5 V L = 744310200
TA = 25°C
Figure 39. Efficiency
TPS54116-Q1 D002_SLVSCO3.gif
Figure 2. Non-switching Supply Current - LDO and Buck Enabled vs Temperature
TPS54116-Q1 D004_SLVSCO3.gif
Figure 4. Non-switching Supply Current - LDO Disabled and Buck Enabled vs Temperature
TPS54116-Q1 D006_SLVSCO3.gif
Figure 6. ENSW and ENLDO Individual Input Current vs Temperature
TPS54116-Q1 D008_SLVSCO3.gif
Figure 8. Voltage Reference vs Temperature
TPS54116-Q1 D010_SLVSCO3.gif
Figure 10. MOSFET Rds(on) vs Temperature
TPS54116-Q1 D012_SLVSCO3.gif
V(PVIN) = 5 V TA = 25°C
Figure 12. High-side Current Limit vs RILIM
TPS54116-Q1 D014_SLVSCO3.gif
i.
Figure 14. Minimum Pulse-width vs Temperature
TPS54116-Q1 D016_SLVSCO3.gif
TA = 25°C
Figure 16. Switching Frequency vs R(RT/SYNC) Low Range
TPS54116-Q1 D018_SLVSCO3.gif
R(RT/SYNC) = 150 kΩ
Figure 18. Switching Frequency vs Temperature
TPS54116-Q1 D020_SLVSCO3.gif
Internal RT
Figure 20. Switching Frequency vs Temperature
TPS54116-Q1 D022_SLVSCO3.gif
V(SS/TRK) > VSS(THR)
Figure 22. I(SS/TRK) vs Temperature
TPS54116-Q1 D024_SLVSCO3.gif
Figure 24. PGOOD Thresholds vs Temperature
TPS54116-Q1 D027_SLVSCO3.gif
VDDQSNS = 1.5 V VIN = 5 V
Figure 26. VTTREF Regulation to VDDQSNS/2 vs I(VTTREF)
TPS54116-Q1 D029_SLVSCO3.gif
VDDQSNS = 1.2 V VIN = 5 V
Figure 28. VTTREF Regulation to VDDQSNS/2 vs I(VTTREF)
TPS54116-Q1 D031_SLVSCO3.gif
VDDQSNS = 1.5 V VIN = 5 V
Figure 30. VTT Regulation to VTTREF vs I(VTT)
TPS54116-Q1 D033_SLVSCO3.gif
VDDQSNS = 1.2 V VIN = 5 V
Figure 32. VTT Regulation to VTTREF vs I(VTT)
TPS54116-Q1 D035_SLVSCO3.gif
V(VTT) = 1.5 V VIN = 5 V I(VTT) = +1 A
TA = 25°C
Figure 34. VTT Sourcing Frequency Response
TPS54116-Q1 D044_SLVSCO3.gif
fSYNC = 2.1 MHz VIN = 3.3 V L = 744373240068
TA = 25°C
Figure 36. Efficiency
TPS54116-Q1 D046_SLVSCO3.gif
fSYNC = 400 kHz VIN = 3.3 V L = 744310200
TA = 25°C
Figure 38. Efficiency
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