10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 65 for a PCB layout example. The GND pin should be tied directly to the power pad under the IC and the power pad.

The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching node, the catch diode and output inductor should be located very close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.

10.2 Layout Example

Figure 65. PCB Layout Example

10.3 Power Dissipation Estimate

The following formulas show how to estimate the device power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM).

The power dissipation of the device includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supply current (Pq).

Equation 54.

Equation 55.

Equation 56.

Equation 57.

where

• I_OUT is the output current (A)
• R_DS(on) is the on-resistance of the high-side MOSFET (Ω)
• V_OUT is the output voltage (V)
• V_IN is the input voltage (V)
• ƒ_SW is the switching frequency (Hz)

Equation 58.

For given T_A,

Equation 59.

For given T_JMAX = 150°C

Equation 60.

where

• P_TOT s the total device power dissipation (W)
• T_A is the ambient temperature (°C)
• T_J is the junction temperature (°C)
• R_TH is the thermal resistance of the package (°C/W)
• T_J(max) is maximum junction temperature (°C)
• T_A(max) is maximum ambient temperature (°C).

There are additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and trace resistance that will impact the overall efficiency of the regulator.