8.4.3 Analog Dimming Mode Operation

Once the analog dimming mode is chosen, the internal voltage reference for the FB pin is approximately 200 mV at full scale, and proportional to the PWM duty cycle as shown in Figure 16. LED current is continuous in this mode, and the current magnitude can be adjusted by changing PWM duty cycle, see Figure 18. Because the internal voltage reference is filtered from the PWM signal, a too-low PWM frequency may cause excessive ripple at the voltage reference. To minimize this ripple, the suggested PWM signal frequency is 10 kHz or higher, such as 50 kHz.

Figure 18. Analog Dimming Operation

A comparator with 400-mV hysteresis is used to generate the internal PWM signal, see Figure 17. This internal PWM duty cycle determines the voltage reference. To make sure the PWM pin signal is correctly identified, the high level of the PWM signal should be higher than 1 V, and the low level should be lower than 0.6 V. Figure 19 shows the relationship between the external PWM and internal PWM signals.