SLVSAU1E May 2011 – August 2016 TPS54228
PRODUCTION DATA.
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | HSOP, SOIC | VSON | ||
| EN | 1 | 1 | I | Enable input control. EN is active high and must be pulled up to enable the device. |
| VFB | 2 | 2 | I | Converter feedback input. Connect to output voltage with feedback resistor divider. |
| VREG5 | 3 | 3 | O | 5.5-V power supply output. A capacitor (typical 1 µF) must be connected to GND. VREG5 is not active when EN is low. |
| SS | 4 | 4 | I | Soft-start control. An external capacitor must be connected to GND. |
| GND | 5 | — | — | Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at a single point. |
| GND | — | 5 | — | Ground pin. Connect sensitive SS and VFB returns to GND at a single point. |
| SW | 6 | 6, 7 | O | Switch node connection between high-side NFET and low-side NFET. |
| VBST | 7 | 8 | I | Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW pins. An internal diode is connected between VREG5 and VBST. |
| VIN | 8 | 9, 10 | I | Input voltage supply pin. |
| Exposed Thermal Pad | Back side(1) | — | — | Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to GND. |
| — | Back side | — | Thermal pad of the package. PGND power ground return of internal low-side FET. Must be soldered to achieve appropriate dissipation. | |