8.3.1 Fixed-Frequency PWM Control

The TPS54232 uses a fixed frequency, peak current mode control. The internal switching frequency of the TPS54232 is fixed at 1 MHz.

8.3.2 Voltage Reference (V_ref)

The voltage reference system produces a ±2% initial accuracy voltage reference (±3.5% over temperature) by scaling the output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.8 V.

8.3.3 Bootstrap Voltage (BOOT)

The TPS54232 has an integrated boot regulator and requires a 0.1-μF ceramic capacitor between the BOOT and PH pin to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS54232 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.1 V typically.

8.3.4 Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)

The EN pin has an internal pull-up current source that provides the default condition of the TPS54232 operating when the EN pin floats.

The TPS54232 is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. It is recommended to use an external VIN UVLO to add hysteresis unless VIN is greater than (V_OUT + 2V). To adjust the VIN UVLO with hysteresis, use the external circuitry connected to the EN pin as shown in Figure 9. Once the EN pin voltage exceeds 1.25 V, an additional 3 μA of hysteresis is added. Use Equation 1 and Equation 2 to calculate the resistor values needed for the desired VIN UVLO threshold voltages. The V_START is the input start threshold voltage, the V_STOP is the input stop threshold voltage and the V_EN is the enable threshold voltage of 1.25 V. The V_STOP should always be greater than 3.5 V.

Figure 9. Adjustable Input Undervoltage Lockout

Equation 1.

Equation 2.

8.3.5 Programmable Slow-Start Using SS Pin

It is highly recommended to program the slow start time externally because no slow start time is implemented internally. The TPS54232 effectively uses the lower voltage of the internal voltage reference or the SS pin voltage as the power supply’s reference voltage fed into the error amplifier and will regulate the output accordingly. A capacitor (C_SS) on the SS pin to ground implements a slow start time. The TPS54232 has an internal pull-up current source of 2 μA that charges the external slow start capacitor. The equation for the slow start time (10% to 90%) is shown in Equation 3. The V_ref is 0.8V and the I_SS current is 2μA.

Equation 3.

The slow start time should be set between 1 ms to 10 ms to ensure good startup behavior. The slow-start capacitor should be no more than 27 nF.

If during normal operation, the input voltage drops below the VIN UVLO threshold, or the EN pin is pulled below 1.25 V, or a thermal shutdown event occurs, the TPS54232 stops switching.

8.3.6 Error Amplifier

The TPS54232 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The transconductance of the error amplifier is 92 μA/V during normal operation. Frequency compensation components are connected between the COMP pin and ground.

8.3.7 Slope Compensation

In order to prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the TPS54232 adds a built-in slope compensation which is a compensating ramp to the switch current signal.

8.3.8 Current Mode Compensation Design

For designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended when doing the stability analysis. This is because the actual ceramic capacitance drops considerably from the nominal value when the applied voltage increases. For the detailed guidelines, see the section.

8.3.9 Overcurrent Protection and Frequency Shift

The TPS54232 implements current mode control that uses the COMP pin voltage to turn off the high-side MOSFET on a cycle by cycle basis. Every cycle the switch current and the COMP pin voltage are compared; when the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, causing the switch current to increase. The COMP pin has a maximum clamp internally, which limit the output current.

The TPS54232 provides robust protection during short circuits. There is potential for overcurrent runaway in the output inductor during a short circuit at the output. The TPS54232 solves this issue by increasing the off time during short circuit conditions by lowering the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 V to 0.8 V on VSENSE pin. The relationship between the switching frequency and the VSENSE pin voltage is shown in Table 1.

8.3.10 Overvoltage Transient Protection

The TPS54232 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin voltage goes above 109% × V_ref, the high-side MOSFET will be forced off. When the VSENSE pin voltage falls below 107% × V_ref, the high-side MOSFET will be enabled again.

8.3.11 Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 165°C, the device reinitiates the power up sequence.

8.4.1 Eco-Mode

The TPS54232 device is designed to operate in pulse skipping Eco-mode at light load currents to boost light load efficiency. When the peak inductor current is lower than 100 mA (typical), the COMP pin voltage falls to 0.5 V (typical) and the device enters Eco-mode . When the device is in Eco-mode, the COMP pin voltage is clamped at 0.5 V internally which prevents the high-side integrated MOSFET from switching. The peak inductor current must rise above 100 mA for the COMP pin voltage to rise above 0.5 V and exit Eco-mode. Because the integrated current comparator catches the peak inductor current only, the average load current entering Eco-mode varies with the applications and external output filters.

8.4.2 Operation With VIN < 3.5 V

The device is recommended to operate with input voltages above 3.5 V. The typical VIN UVLO threshold is not specified and the device can operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage, the device does not switch. If the EN pin is externally pulled up or left floating, the device becomes active when the VIN pin passes the UVLO threshold. Switching begins when the slow-start sequence is initiated.

8.4.3 Operation With EN Control

The enable threshold voltage is 1.25 V (typical). With the EN pin is held below that voltage the device is disabled and switching is inhibited even if the VIN pin is above the UVLO threshold. The IC quiescent current is reduced in this state. If the EN voltage increases above the threshold while the VIN pin is above the UVLO threshold, the device becomes active. Switching is enabled, and the slow-start sequence is initiated.