Table 3. Design Parameters

DESIGN PARAMETER	EXAMPLE VALUE
Input voltage range	8 V to 18 V
Output voltage	3.3 V
Input ripple voltage	300 mV
Output ripple voltage	100 mV
Output current rating	2 A
Operating Frequency	300 kHz

9.2.2.1 Switching Frequency

The switching frequency for the TPS54233 is fixed at 300 kHz.

9.2.2.2 Output Voltage Set Point

The output voltage of the TPS54233 is externally adjustable using a resistor divider network. In the application circuit of Figure 12, this divider network is comprised of R5 and R6. The relationship of the output voltage to the resistor divider is given by Equation 4 and Equation 5:

Choose R5 to be approximately 10 kΩ. Slightly increasing or decreasing R5 can result in closer output voltage matching when using standard value resistors. In this design, R5 = 10.2 kΩ and R6 = 3.24 kΩ, resulting in a
3.31 V output voltage.

9.2.2.3 Input Capacitors

The TPS54233 requires an input decoupling capacitor and depending on the application, a bulk input capacitor. The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is recommended. The voltage rating should be greater than the maximum input voltage. A smaller value may be used as long as all other requirements are met; however 10 μF has been shown to work well in a wide variety of circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54233 circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple voltage is acceptable. For this design two 4.7 μF capacitors are used for the input decoupling capacitor. They are X7R dielectric rated for 50 V. The equivalent series resistance (ESR) is approximately 2 mΩ, and the current rating is 3 A. Additionally, a small 0.01 μF capacitor is included for high frequency filtering.

This input ripple voltage can be approximated by Equation 6

Where I_OUT(MAX) is the maximum load current, f_SW is the switching frequency, C_BULK is the bulk capacitor value and ESR_MAX is the maximum series resistance of the bulk capacitor.

The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be approximated by Equation 7

In this case, the input ripple voltage would be 143 mV and the RMS ripple current would be 1.5 A. It is also important to note that the actual input voltage ripple will be greatly affected by parasitics associated with the layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is shown in Design Parameters and is larger than the calculated value. This measured value is still below the specified input limit of 300 mV. The maximum voltage across the input capacitors would be VIN max plus ΔVIN/2. The chosen bulk and bypass capacitors are each rated for 50 V and the ripple current capacity is greater than 3 A, both providing ample margin. It is important that the maximum ratings for voltage and current are not exceeded under any circumstance.

9.2.2.4 Output Filter Components

Two components need to be selected for the output filter, L1 and C9. Since the TPS54233 is an externally compensated device, a wide range of filter component types and values can be supported.

9.2.2.5 Compensation Components

The external compensation used with the TPS54233 allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R dielectric output capacitors, but other types are supported.

A Type II compensation scheme is recommended for the TPS54233. The compensation components are chosen to set the desired closed loop cross over frequency and phase margin for output filter components. The type II compensation has the following characteristics; a dc gain component, a low frequency pole, and a mid frequency zero / pole pair.

The dc gain is determined by Equation 15:

Where:

V_ggm = 800
V_REF = 0.8 V

The low-frequency pole is determined by Equation 16:

The mid-frequency zero is determined by Equation 17:

And, the mid-frequency pole is given by Equation 18:

The first step is to choose the closed loop crossover frequency. In general, the closed-loop crossover frequency should be less than 1/8 of the minimum operating frequency, but for the TPS54233it is recommended that the maximum closed loop crossover frequency be not greater than 25 kHz. Next, the required gain and phase boost of the crossover network needs to be calculated. By definition, the gain of the compensation network must be the inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is less than the closed loop crossover frequency, the gain of the modulator and output filter can be approximated by Equation 19:

Where:

R_SENSE = 1Ω/9

R_O = V_O/I_O

R_ESR = Equivalent series resistance of the output capacitor

The phase loss is given by Equation 20:

Where:

R_ESR = Equivalent series resistance of the output capacitor

R_O = V_O/I_O

Now that the phase loss is known the required amount of phase boost to meet the phase margin requirement can be determined. The required phase boost is given by Equation 21:

Where PM = the desired phase margin.

A zero / pole pair of the compensation network will be placed symmetrically around the intended closed loop frequency to provide maximum phase boost at the crossover point. The amount of separation can be determined by Equation 22 and the resultant zero and pole frequencies are given by Equation 23 and Equation 24

The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the modulator and output filter. Due to the relationships established by the pole and zero relationships, the value of R_Z can be derived directly by Equation 25 :

Where:

V_O = Output voltage

R_OA = 8.696 MΩ

GM_COMP = 9 A/V

V_ggm = 800

V_REF = 0.8 V

R_ESR = Equivalent series resistance of the output capacitor

With R_Z known, C_Z and C_P can be calculated using Equation 26 and Equation 27:

For this design, a singe 470 μF output capacitor is used. The ESR is approximately .160 Ω. The desired closed loop crossover frequency is 22000 Hz.

Using Equation 19 and Equation 20, the output stage gain and phase loss are equivalent as:

Gain = –3.114 dB

and

PL = –4.96 degrees

For 60 degrees of phase margin, Equation 21 requires no additional phase boost, so K can be set equal to 1.

Equation 22, Equation 23, and Equation 24 are used to find the zero and pole frequencies of:

F_Z1 = 22000 Hz

And

F_P1 = 22000 Hz

R_Z, C_Z, and C_P are calculated using Equation 25, Equation 26, and Equation 27:

Using standard values for R3, C6, and C7 in the application schematic of Figure 12:

R3 = 30.9 kΩ

C6 = 220 pF

C7 = 220 pF

The measured overall loop response for the circuit is given in Figure 12. Note that the actual closed loop crossover frequency is higher than intended at about 25 kHz. This is primarily due to variation in the actual values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of line and load variability.

9.2.2.6 Bootstrap Capacitor

Every TPS54233 design requires a bootstrap capacitor, C4. The bootstrap capacitor must be 0.1 μF. The bootstrap capacitor is located between the PH pins and BOOT pin. The bootstrap capacitor should be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.

9.2.2.7 Catch Diode

The TPS54233 is designed to operate using an external catch diode between PH and GND. The selected diode must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum voltage at the PH pin, which is V_INMAX + 0.5 V. Peak current must be greater than I_OUTMAX plus on half the peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage of 40 V, forward current of 3 A, and a forward voltage drop of 0.5 V.

9.2.2.8 Output Voltage Limitations

Due to the internal design of the TPS54233, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 91% and is given by Equation 31:

Where:

V_{IN min} = Minimum input voltage

I_{O max} = Maximum load current

V_D = Catch diode forward voltage

R_L = Output inductor series resistance

The equation assumes maximum on resistance for the internal high-side FET.

The lower limit is constrained by the minimum controllable on time which may be as high as 160 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by Equation 32:

Where:

V_{IN max} = Maximum input voltage

I_{O min} = Minimum load current

V_D = Catch diode forward voltage

R_L = Output inductor series resistance

This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device should be carefully checked to assure proper functionality.

9.2.2.9 Power Dissipation Estimate

The following formulas show how to estimate the device power dissipation under continuous conduction mode operations. They should not be used if the device is working in the discontinuous conduction mode (DCM) or pulse skipping Eco-mode^TM.

The device power dissipation includes:

1) Conduction loss: Pcon = Iout² x R_DS(on) x V_OUT/VIN

2) Switching loss: Psw = 0.5 x 10^-9 x VIN² x I_OUT x Fsw

3) Gate charge loss: Pgc = 22.8 x 10^-9 x Fsw

4) Quiescent current loss: Pq = 0.075 x 10^-3 x VIN

Where:

I_OUT is the output current (A).

R_DS(on) is the on-resistance of the high-side MOSFET (Ω).

V_OUT is the output voltage (V).

VIN is the input voltage (V).

Fsw is the switching frequency (Hz).

So

Ptot = Pcon + Psw + Pgc + Pq

For given T_A , T_J = T_A + Rth x Ptot.

For given T_JMAX = 150°C, T_AMAX = T_JMAX– Rth x Ptot.

Where:

Ptot is the total device power dissipation (W).

T_A is the ambient temperature (°C).

T_J is the junction temperature (°C) .

Rth is the thermal resistance of the package (°C/W).

T_JMAX is maximum junction temperature (°C).

T_AMAX is maximum ambient temperature (°C).