ZHCS338D October 2011 – August 2016 TPS54295
PRODUCTION DATA.
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | HTSSOP | VQFN | ||
| EN1 | 5 | 7 | I | Enable. Pull high to enable the corresponding (1 or 2) converter. |
| EN2 | 12 | 14 | ||
| GND | 8 | 10 | I/O | Signal GND. Connect sensitive SSx and VFBx returns to GND at a single point. |
| PGND1 | 4 | 6 | I/O | Ground returns for low-side MOSFETs. Input of current comparator. |
| PGND2 | 13 | 15 | ||
| SS1 | 6 | 8 | O | Soft-start programming pin. Connect capacitor from SSx pin to GND to program soft-start time. |
| SS2 | 11 | 13 | ||
| SW1 | 3 | 5 | I/O | Switch node connections for both the high-side NFETs and low-side NFETs. Input of current comparator. |
| SW2 | 14 | 16 | ||
| VBST1 | 2 | 14 | I | Supply input for high-side NFET gate drive circuit. Connect a 0.1-µF ceramic capacitor between VBSTx and SWx pins. An internal diode is connected between VREG5 and VBSTx. |
| VBST2 | 15 | 1 | ||
| VFB1 | 7 | 9 | I | D-CAP2 feedback inputs. Connect to output voltage with resistor divider. |
| VFB2 | 10 | 12 | ||
| VIN1 | 1 | 3 | I | Power inputs and connects to both high-side NFET drains. Supply Input for 5.5-V linear regulator. |
| VIN2 | 16 | 2 | ||
| VREG5 | 9 | 11 | O | Output of 5.5-V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least 1 µF. VREG5 is active when VIN1 is added. |
| Thermal Pad | — | — | — | Thermal pad of the package. Must be soldered to ground to achieve appropriate dissipation. Must be connected to GND. |