The TPS542A50 has 15 unique internal compensation settings to cover a wide range of output inductors and capacitors. For each switching frequency option, there are four compensation options that can be chosen using a single resistor to ground on the COMP pin or through I²C programming.

In addition to selecting the compensation option, the COMP pin also selects the device I²C address. The following compensation settings and I²C address combinations can be programmed on the COMP pin.

Each compensation network consists of two zeros and one high frequency pole. Table 7-3 maps the compensation settings to the first zero frequency at different output voltage range, second zero frequency, and high frequency pole.

Table 7-4 shows the second zero frequency placement about two times based on a ratio (f_O/f_SW) of the LC frequency (f_O) to the switching frequency and lists the values in Table 7-3. The second zero frequency does not change with the output voltage. The high frequency pole is about 10 times of the second zero frequency to attenuate the switching frequency noise and to have a safe gain margin.

The output filter LC frequency must be designed between the first and second zero frequencies. The ratio of the LC frequency to the switching frequency in Table 7-4 is a guide to select the LC frequency f_O. For example, the LC frequency for 1-MHz switching frequency is 10 kHz at 1% ratio. Given 1-V output voltage, COMP2 has the first zero at 4.5 kHz to compensate the LC filter double poles. For the same LC filter and switching frequencies of 3.3-V output voltage, COMP3 has the first zero at 6.7 kHz to compensate the LC filter double poles. The compensation setting needs to consider for the output capacitor derating, especially ceramic capacitor, and inductor tolerance. It is recommended to verify the load transient and bode plot based upon the compensation selection.