ZHCSM62C September   2020  – December 2021 TPS542A50

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Adjustable Undervoltage Lockout
      2. 7.3.2  Input and VREG Undervoltage Lockout Protection
      3. 7.3.3  Voltage Reference and Setting the Output Voltage
      4. 7.3.4  Remote Sense Function
      5. 7.3.5  Switching Frequency
      6. 7.3.6  Voltage Control Mode Internal Compensation
      7. 7.3.7  Soft Start and Prebiased Output Start-up
      8. 7.3.8  Power Good
      9. 7.3.9  Overvoltage and Undervoltage Protection
      10. 7.3.10 Overcurrent Protection
      11. 7.3.11 High-Side FET Throttling
      12. 7.3.12 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse-Frequency Modulation Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Soft Start
    5. 7.5 Programming
      1. 7.5.1 I2C Address Selection
      2. 7.5.2 Powering Device Into Programming Mode
      3. 7.5.3 Device Configuration
      4. 7.5.4 Output Voltage Adjustment
    6. 7.6 Pin-Strap Programming
    7. 7.7 Register Maps
      1. 7.7.1 ID Register (Offset = 0x0) [reset = 0x21]
      2. 7.7.2 STATUS Register (Offset = 0x1) [reset = 0x0]
      3. 7.7.3 VOUT_ADJ1 Register (Offset = 0x2) [reset = 0x0]
      4. 7.7.4 VOUT_ADJ2 Register (Offset = 0x3) [reset = 0x0]
      5. 7.7.5 CONFIG1 Register (Offset = 0x4) [reset = 0x0B]
      6. 7.7.6 CONFIG2 Register (Offset = 0x5) [reset = 0x2D]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Full Analog Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Output Voltage Calculation
          3. 8.2.1.2.3  Switching Frequency Selection
          4. 8.2.1.2.4  Inductor Selection
          5. 8.2.1.2.5  Input Capacitor Selection
          6. 8.2.1.2.6  Bootstrap Capacitor Selection
          7. 8.2.1.2.7  R-C Snubber and VIN Pin High-Frequency Bypass
          8. 8.2.1.2.8  Output Capacitor Selection
          9. 8.2.1.2.9  Response to a Load Transient
          10. 8.2.1.2.10 Pin-Strap Setting
        3. 8.2.1.3 Application Curves
        4. 8.2.1.4 Typical Application Circuits
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Fusion Digital Power™ Designer Tool
        2. 11.1.1.2 Custom Design With WEBENCH® Tools
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

GUID-B05E7472-17D1-40A0-B05D-853C6E42B366-low.gif Figure 5-1 33-Pin VQFN RJM Package (Top View)
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
AGND 8, 25 G Ground of the internal analog and digital circuitry
AVIN 21 P Power input to the controller. Tie this pin to PVIN. It is best to use an RC filter from PVIN such as 10 Ω and 100 nF to 1 μF.
BOOT 17 P Gate drive voltage for high-side FET. Connect a bootstrap capacitor between this pin and SW.
COMP 24 I A resistor to ground sets the I2C address and compensation network. This pin can be grounded to select the default compensation and reduce BOM count.
EN 22 I Enable pin. Float to enable, enable/disable with an external signal, or adjust the input undervoltage lockout with a resistor divider.
FSEL 23 I A resistor to ground sets the switching frequency of the converter. This pin can be grounded to select the default switching frequency to reduce BOM count.
ILIM 1 I A resistor to ground sets the overcurrent protection limit. This pin can be grounded to select default settings and reduce BOM count.
PGD 11 O Open-drain power good status
PGND 13-16, 29-33 G Power ground. These pins are internally connected to the return of the internal low-side FET.
PVIN 18-20 P Power inputs to the power stage. Low impedance bypassing of these pins to PGND is critical. At least 10 nF to 100 nF capacitor from PVIN to PGND is required.
RSN 6 I Remote sense ground return
RSP 7 I Remote sense connection to VOUT
SCL 3 I Clock input for I2C programming
SDA 4 I/O Data input for I2C programming
SREF 10 O 1.2-V nominal system reference
SS/PFM 2 I A resistor to ground sets the soft-start slew rate and PFM mode. To reduce BOM count this pin can be grounded to use the default soft-start rate and enable PFM mode.
SYNC 5 I In shutdown mode, an active high puts the IC into programming mode. In operation, this pin is a clock input for synchronizing the oscillator.
SW 26-28 O Switch node output of the converter. Connect this pin to the output inductor.
VREG 12 I/O Bypass pin for the internal power stage LDO. It is recommended to use 4.7-μF ceramic capacitor to ground.
VSET 9 I Output voltage reference for the control loop. This must be the mid-point of a resistive divider from SREF to AGND. Set this voltage to be 1/5 of the desired VOUT.
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