米6体育平台手机版

ZHCSSP5D January 2009 – September 2023 TPS54332

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

DDA|8
- MPDS092F

散热焊盘机械数据 (封装 | 引脚)

DDA|8
- PPTD087E

订购信息

8.2.2.11 Output Voltage Limitations

Due to the internal design of the TPS54332, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 91% and is given by Equation 32.

Equation 32.

V_{O (M A X)} = 0.91 \times ((V_{I N (M I N)} - I_{O (M A X)} \times R_{D S (O N) M A X}) + V_{D}) - (I_{O (M A X)} \times R_{L}) - V_{D}

Where:

V_IN(min) = Minimum input voltage

I_O(max) = Maximum load current

V_D = Catch diode forward voltage

R_L = Output inductor series resistance

The equation assumes maximum on resistance for the internal high-side FET.

The lower limit is constrained by the minimum controllable on time which can be as high as 130 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by Equation 33.

Equation 33.

V_{O (M I N)} = 0.118 \times ((V_{I N (M A X)} - I_{O (M I N)} \times R_{D S (O N) M A X} + V_{D}) - I_{O (M I N)} \times R_{L}) - V_{D}

Where:

V_IN(max) = Maximum input voltage

I_O(min) = Minimum load current

V_D = Catch diode forward voltage

R_L = Output inductor series resistance

This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device must be carefully checked to assure proper functionality.