10.1 Layout Guidelines

The VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the IC. The typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN and GND pins of the device. See Figure 55 for a PCB layout example. The GND pin should be tied to the PCB ground plane at the pin of the IC. To facilitate close placement of the input bypass capacitors, the PH pin should be routed to a small copper area directly adjacent to the pin. Use vias to route the PH signal to the bottom side or an inner layer. If necessary, allow the top-side copper area to extend slightly under the body of the closest input bypass capacitor. Make the copper trace on the bottom or internal layer short and wide as practical to reduce EMI issues. Connect the trace with vias back to the top side to connect with the output inductor as shown after the GND pin. In the same way use a bottom or internal layer trace to route the PH signal across the VIN pin to connect to the boot capacitor as shown. Make the circulating loop from the PH pin to the output inductor and output capacitors and then back to GND as tight as possible while preserving adequate etch width to reduce conduction losses in the copper . For operation at a full rated load, the ground area near the IC must provide adequate heat dissipating area. Connect the exposed thermal pad to the bottom or internal layer ground plane using vias as shown. Additional vias may be used adjacent to the IC to tie top-side copper to the internal or bottom layer copper. The additional external components can be placed approximately as shown. Use a separate ground trace to connect the feedback, compensation, UVLO, and RT (SS for TPS54336A) returns. Connect this ground trace to the main power ground at a single point to minimize circulating currents. Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been shown to produce good results and is intended as a guideline.

10.2 Layout Example

NOTE:

Pin 8 for the TPS54336A device is SS. Connect an SS capacitor instead of an RT resistor from pin 8 to GND.

Figure 55. TPS54335ADDA Board Layout