SUPPLY VOLTAGE (VIN PIN) |
|
Operating input voltage |
|
4.5 |
|
42 |
V |
|
Internal undervoltage lockout threshold |
Rising |
4.1 |
4.3 |
4.48 |
V |
|
Internal undervoltage lockout threshold hysteresis |
|
|
325 |
|
mV |
|
Shutdown supply current |
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V |
|
2.25 |
4.5 |
μA |
|
Operating: nonswitching supply current |
FB = 0.9 V, TA = 25°C |
|
152 |
200 |
ENABLE AND UVLO (EN PIN) |
|
Enable threshold voltage |
No voltage hysteresis, rising and falling |
1.1 |
1.2 |
1.3 |
V |
|
Input current |
Enable threshold = 50 mV |
|
–4.6 |
|
μA |
Enable threshold = –50 mV |
–0.58 |
–1.2 |
–1.8 |
|
Hysteresis current |
|
–2.2 |
–3.4 |
–4.5 |
μA |
|
Enable to COMP active |
VIN = 12 V, TA = 25°C |
|
540 |
|
µs |
VOLTAGE REFERENCE |
|
Voltage reference |
|
0.792 |
0.8 |
0.808 |
V |
HIGH-SIDE MOSFET |
|
On-resistance |
VIN = 12 V, BOOT-SW = 6 V |
|
87 |
185 |
mΩ |
ERROR AMPLIFIER |
|
Input current |
|
|
50 |
|
nA |
|
Error amplifier transconductance (gm) |
–2 μA < ICOMP < 2 μA, VCOMP = 1 V |
|
350 |
|
μMhos |
|
Error amplifier transconductance (gm) during soft-start |
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V |
|
77 |
|
μMhos |
|
Error amplifier DC gain |
VFB = 0.8 V |
|
10000 |
|
V/V |
|
Min unity gain bandwidth |
|
|
2500 |
|
kHz |
|
Error amplifier source and sink |
V(COMP) = 1 V, 100-mV overdrive |
|
±30 |
|
μA |
|
COMP to SW current transconductance |
|
|
12 |
|
A/V |
CURRENT LIMIT |
|
Current limit threshold |
All VIN and temperatures, open loop(1) |
4.5 |
5.5 |
6.8 |
A |
All temperatures, VIN = 12 V, open loop(1) |
4.5 |
5.5 |
6.3 |
VIN = 12 V, TA = 25°C, open loop(1) |
5.2 |
5.5 |
5.9 |
|
Current limit threshold delay |
|
|
60 |
|
ns |
THERMAL SHUTDOWN |
|
Thermal shutdown |
|
|
176 |
|
°C |
|
Thermal shutdown hysteresis |
|
|
12 |
|
°C |
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) |
|
Switching frequency range using RT mode |
|
100 |
|
2500 |
kHz |
ƒSW |
Switching frequency |
RT = 200 kΩ |
450 |
500 |
550 |
kHz |
|
Switching frequency range using CLK mode |
|
160 |
|
2300 |
kHz |
|
Minimum CLK input pulse width |
|
|
15 |
|
ns |
|
RT/CLK high threshold |
|
|
1.55 |
2 |
V |
|
RT/CLK low threshold |
|
0.5 |
1.2 |
|
V |
|
RT/CLK falling edge to SW rising edge delay |
Measured at 500 kHz with RT resistor in series |
|
55 |
|
ns |
|
PLL lock in time |
Measured at 500 kHz |
|
78 |
|
μs |
SOFT START AND TRACKING (SS/TR PIN) |
|
Charge current |
VSS/TR = 0.4 V |
|
1.7 |
|
µA |
|
SS/TR-to-FB matching |
VSS/TR = 0.4 V |
|
42 |
|
mV |
|
SS/TR-to-reference crossover |
98% nominal |
|
1.16 |
|
V |
|
SS/TR discharge current (overload) |
FB = 0 V, VSS/TR = 0.4 V |
|
354 |
|
µA |
|
SS/TR discharge voltage |
FB = 0 V |
|
54 |
|
mV |
POWER GOOD (PWRGD PIN) |
|
FB threshold for PWRGD low |
FB falling |
|
90% |
|
|
|
FB threshold for PWRGD high |
FB rising |
|
93% |
|
|
|
FB threshold for PWRGD low |
FB rising |
|
108% |
|
|
|
FB threshold for PWRGD high |
FB falling |
|
106% |
|
|
|
Hysteresis |
FB falling |
|
2.5% |
|
|
|
Output high leakage |
VPWRGD = 5.5 V, TA = 25°C |
|
10 |
|
nA |
|
On resistance |
IPWRGD = 3 mA, VFB < 0.79 V |
|
45 |
|
Ω |
|
Minimum VIN for defined output |
VPWRGD < 0.5 V, IPWRGD = 100 µA |
|
0.9 |
2 |
V |