ZHCSG10 February   2017 TPS54360B-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-Mode™
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Internal Soft-Start
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
      10. 7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
      11. 7.3.11 Synchronization to RT/CLK Pin
      12. 7.3.12 Overvoltage Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Small Signal Model for Loop Response
      15. 7.3.15 Simple Small Signal Model for Peak Current Mode Control
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation near Minimum VIN (VVIN = < 4.5 V)
      2. 7.4.2 Operation with EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 5-V Output TPS54360B-Q1 Design Example
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Selecting the Switching Frequency
          2. 8.2.1.2.2  Output Inductor Selection (LO)
          3. 8.2.1.2.3  Output Capacitor
          4. 8.2.1.2.4  Catch Diode
          5. 8.2.1.2.5  Input Capacitor
          6. 8.2.1.2.6  Bootstrap Capacitor Selection
          7. 8.2.1.2.7  Undervoltage Lockout Set Point
          8. 8.2.1.2.8  Output Voltage and Feedback Resistors Selection
          9. 8.2.1.2.9  Minimum VIN
          10. 8.2.1.2.10 Compensation
          11. 8.2.1.2.11 Discontinuous Conduction Mode and Eco-Mode™ Boundary
          12. 8.2.1.2.12 Power Dissipation Estimate
        3. 8.2.1.3 Application Curves
      2. 8.2.2 TPS54360B-Q1 Inverting Power Supply
      3. 8.2.3 TPS54360B-Q1 Split Rail Power Supply
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimated Circuit Area
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 Third-Party Products Disclaimer
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DDA Package
HSOP (8 Pin)
(Top View)

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BOOT 1 O A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the minimum required to operate the high-side MOSFET, the output is switched off until the capacitor is refreshed.
VIN 2 I Input supply voltage with 4.5-V to 60-V operating range.
EN 3 I Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
RT/CLK 4 I Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
FB 5 I Inverting input of the transconductance (gm) error amplifier.
COMP 6 O Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency compensation components to this pin.
GND 7 – Ground
SW 8 I The source of the internal high-side power MOSFET and switching node of the converter.
Thermal Pad – – GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |