7.3.15 Simple Small Signal Model for Peak-Current-Mode Control

Figure 29 describes a simple small signal model that can be used to design the frequency compensation. The TPS54360B power stage can be approximated by a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 11 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 28) is the power stage transconductance, gm_PS. The gm_PS for the TPS54360B is 12 A/V. The low-frequency gain of the power stage is the product of the transconductance and the load resistance as shown in Equation 12.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 13). The combined effect is highlighted by the dashed line in the right half of Figure 29. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same with varying load conditions. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 14).

Figure 29. Simple Small Signal Model and Frequency Response for Peak-Current-Mode Control

Equation 11.

Equation 12.

Equation 13.

Equation 14.