ZHCSGJ0B May 2017 – March 2018 TPS543B20
PRODUCTION DATA.
The TPS543B20 device implements an unique clock sync scheme for phase interleaving during stackable configuration. The device will receive the clock through sync pin and generate sync points for another TPS543B20 device to sync to one of them to achieve phase interleaving. Sync point options can be selected through RT pin when 1) device is configurated as master sync in, 2) device is configured as slave. See Table 5 for Control Mode Selection.
CLOCK SYNC OPTIONS | RESISTOR VALUE (kΩ) |
0 (0° Interleaving) | 0 |
1/4 (90° Interleaving) | 8.66 |
1/3 (120° Interleaving) | 15.4 |
2/3 (240° Interleaving) | 23.7 |
3/4 (270° Interleaving) | 34.8 |
1/2 (180° Interleaving) | OPEN |