ZHCSG52B March 2017 – May 2018 TPS543C20
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 Soft-Start Operation
- 8.4.2 Input and VDD Undervoltage Lockout (UVLO) Protection
- 8.4.3 Power Good and Enable
- 8.4.4 Voltage Reference
- 8.4.5 Prebiased Output Start-up
- 8.4.6 Internal Ramp Generator
- 8.4.7 Switching Frequency
- 8.4.8 Clock Sync Point Selection
- 8.4.9 Synchronization and Stackable Configuration
- 8.4.10 Dual-Phase Stackable Configurations
- 8.4.11 Operation Mode
- 8.4.12 API/BODY Brake
- 8.4.13 Sense and Overcurrent Protection
- 8.4.14 Output Overvoltage and Undervoltage Protection
- 8.4.15 Overtemperature Protection
- 8.4.16 RSP/RSN Remote Sense Function
- 8.4.17 Current Sharing
- 8.4.18 Loss of Synchronization
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application: TPS543C20 Stand-alone Device
- 9.2.1 Design Requirements
- 9.2.2 Detailed Design Procedure
- 9.2.3 Application Curves
- 9.3 System Example
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
8.4.18 Loss of Synchronization
During sync clock condition, each individual converter will continuously compare current falling edge and previous falling edge, if current falling edge exceeded a 1us delay versus previous pulse, converter will declare a lost sync fault, and response by pulling down ISHARE to shut down all phases.
Figure 24. Switching Response When Sync Clock Lost