ZHCSI04E September 2009 – April 2018 TPS54418
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY VOLTAGE (VIN) | ||||||
| VVIN | Operating input voltage | 2.95 | 6 | V | ||
| VUVLO | Internal under voltage lockout threshold | No voltage hysteresis, rising and falling | 2.6 | 2.8 | V | |
| IQ(vin) | Shutdown supply current | VEN = 0 V, TA = 25°C, 2.95 V ≤ VVIN ≤ 6 V | 2 | 5 | μA | |
| Iq | Quiescent current | VVSENSE = 0.9 V, VVIN = 5 V, 25°C,
RT = 400 kΩ |
350 | 500 | μA | |
| ENABLE AND UVLO (EN) | ||||||
| VTH(en) | Enable threshold | Rising | 1.16 | 1.25 | 1.37 | V |
| Falling | 1.18 | |||||
| IEN | Input current | Enable rising threshold + 50 mV | –3.2 | μA | ||
| Enable falling threshold – 50 mV | –0.65 | |||||
| VOLTAGE REFERENCE (VSENSE) | ||||||
| VREF | Voltage reference | 2.95 V ≤ VVIN ≤ 6 V, –40°C <TJ< 150°C | 0.795 | 0.803 | 0.811 | V |
| MOSFET | ||||||
| RDS(HFET) | High-side switch resistance | (VBOOT – VPH) = 5 V | 30 | 60 | mΩ | |
| (VBOOT – VPH) = 2.95 V | 44 | 70 | ||||
| RDS(LFET) | Low-side switch resistance | VVIN = 5 V | 30 | 60 | mΩ | |
| VVIN = 2.95 V | 44 | 70 | ||||
| ERROR AMPLIFIER | ||||||
| IIN | Input current | 7 | nA | |||
| gM(ea) | Error amplifier transconductance | –2 μA < ICOMP< 2 μA, VCOMP = 1 V | 225 | μS | ||
| gm(EA,ss) | Error amplifier transconductance during soft-start | –2 μA < ICOMP< 2 μA, VCOMP = 1 V,
VVSENSE = 0.4 V |
70 | μS | ||
| ICOMP | Error amplifier source/sink | VCOMP = 1 V, 100 mV overdrive | ±20 | μA | ||
| gM | COMP to ISWITCH transconductance | 13 | A/V | |||
| CURRENT LIMIT | ||||||
| ILIM | Current limit threshold | Instantaneous peak current | 5.0 | 6.4 | A | |
| THERMAL SHUTDOWN | ||||||
| TSD | Thermal Shutdown | 175 | °C | |||
| TSD(hyst) | Hysteresis | 15 | °C | |||
| TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK) | ||||||
| fSW | Switching frequency range using RT mode | 200 | 2000 | kHz | ||
| fSW | Switching frequency | RRT = 400 kΩ | 400 | 500 | 600 | kHz |
| fSW | Switching frequency range using CLK mode | 300 | 2000 | kHz | ||
| tMIN(CLK) | Minimum CLK pulse width | 75 | ns | |||
| VRT/CLK | RT/CLK voltage | RRT/CLK = 400 kΩ | 0.5 | V | ||
| VIH(CLK) | RT/CLK high threshold | 1.6 | 2.2 | V | ||
| VIL(CLK) | RT/CLK low threshold | 0.4 | 0.6 | V | ||
| tDLY | RT/CLK falling edge to PH rising edge delay | fSW = 500 kHz with RRT resistor in series | 90 | ns | ||
| tLOCK(PLL) | PLL lock-in time | fSW = 500 kHz | 14 | μs | ||
| HIGH-SIDE POWER MOSFET (PH) | ||||||
| tON(min) | Minimum on time | Measured at 50% points on PH, IOUT = 4 | 60 | ns | ||
| Measured at 50% points on PH, VVIN = 5 V,
IOUT = 0 A |
110 | |||||
| tOFF(min) | Minimum off time | Prior to skipping off pulses,
(VBOOT – VPH) = 2.95 V, IOUT = 4 |
60 | ns | ||
| tRISE | Rise time | VVIN = 5 V | 1.5 | V/ns | ||
| tFALL | Fall time | VVIN = 5 V | 1.5 | V/ns | ||
| BOOT (BOOT) | ||||||
| RBOOT | BOOT charge resistance | VVIN = 5 V | 16 | Ω | ||
| VUVLO(Boot) | BOOT-PH UVLO | VVIN = 2.95 V | 2.1 | V | ||
| SOFT-START (SS ) | ||||||
| ICHG | Charge current | VSS = 0.4 V | 1.8 | μA | ||
| VSSxREF | SS to reference crossover | 98% nominal | 0.9 | V | ||
| VDSCHG(SS) | SS discharge voltage (overload) | VVSENSE = 0 V | 20 | μA | ||
| IDSCHG(SS) | SS discharge current (UVLO, EN, thermal fault) | VVIN = 5 V, VSS = 0.5 V | 1.25 | mA | ||
| POWER GOOD (PWRGD) | ||||||
| VTH(PG) | VSENSE threshold | VVSENSE falling (fault) | 91% | VREF | ||
| VVSENSE rising (good) | 93% | |||||
| VVSENSE rising (fault) | 107% | |||||
| VVSENSE falling (Good) | 105% | |||||
| VHYST(PG) | Hysteresis | VVSENSE falling | 2% | |||
| IPH(lkg) | Output high leakage | VVSENSE = VREF, VPWRGD = 5.5 V | 2 | nA | ||
| RPG | Power Good on-resistance | 100 | Ω | |||
| VOL | Low-level output voltage | IPWRGD = 3.5 mA | 0.3 | V | ||
| VMIN(PG) | Minimum input voltage for valid output | VPWRGD< 0.5 V , IOUT = 100 μA | 1.2 | 1.6 | V | |