10.1 Layout Guidelines

• VIN and PGND traces should be as wide as possible to reduce trace impedance and improve heat dissipation.
• At least 1 µF of input capacitance is required on both VIN pins of the IC and must be placed as close as possible to the IC. The input capacitors must connect directly to the adjacent PGND pins.
• It is recommended to use a ground plane directly below the IC to connect the PGND pins on both sides of the IC together.
• The PGND trace between the output capacitor and the PGND pin should be as wide as possible to minimize its trace impedance.
• Provide sufficient vias for the input capacitor and output capacitor.
• Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
• A separate VOUT path should be connected to the upper feedback resistor.
• Voltage feedback loop should be placed away from the high-voltage switching trace. It is preferable to use ground copper near it as a shield.
• The trace connected to the FB node should be as small as possible to avoid noise coupling.
• Place components connected to the RT/CLK, FB, COMP and SS/TRK pins as close to the IC as possible and minimize traces connected to these pins to avoid noise coupling.
• AGND must be connected to PGND on the PCB. Connect AGND to PGND in a region away from switching currents.

10.2 Layout Example

Figure 54 through Figure 57 shows an example PCB layout and the following list provides a description of each layer.

• The top layer has all components and the main traces for VIN, SW, VOUT and PGND. Both VIN pins are bypassed with two input capacitors placed as close as possible to the IC and are connected directly to the adjacent PGND pins. Multiple vias are placed near the input and output capacitors. The AGND trace is connected to PGND with a wide trace away from the input capacitors to minimize switching noise.
• Midlayer 1 has a solid PGND plane to connect the PGND pins on both sides of the IC together with the shortest path possible and to aid with thermal performance.
• Midlayer 2 has a wide trace connecting both VIN pins of the IC. It is also used to route the BOOT pin to the BOOT-SW capacitor (CBT). It also has a parallel trace for VOUT to minimize trace resistance. The rest of this layer is covered with PGND.
• The bottom layer has the trace connecting the FB resistor divider to VOUT at the point of regulation. PGND is filled into the rest of this layer to aid with thermal performance.

10.3 Alternate Layout Example

Figure 58 through Figure 61 shows an alternate example PCB layout with unsymmetrical placement of the input capacitors and output capacitors. Both VIN pins are still bypassed to their adjacent PGND pins with an input capacitor placed as close as possible to the IC. When using this alternate layout, CI2 should be increased to 1 µF.