8.3.1 Linear Regulators BP3 and BP6

The TPS544x25 devices have two on-board linear regulators to provide suitable power for the internal circuitry of the device. Externally bypass pins BP3 and BP6 for the converter to function properly. BP3 requires a minimum of 2.2 µF of capacitance connected to AGND. BP6 requires a minimum 2.2 µF of capacitance connected to GND. TI recommends using a 4.7-µF capacitor and an additional 100-nF to reduce the ripple on the BP6 pin.

The use of the internal regulators to power other circuits are not recommended because the loads placed on the regulators might adversely affect operation of the controller.

8.3.2 Input Undervoltage Lockout (UVLO)

The TPS544x25 devices provide flexible user adjustment of the undervoltage lockout threshold and hysteresis. Two PMBus commands, VIN_ON (35h) and VIN_OFF (36h) allow the user to set these input voltage turn-on and turn-off thresholds independently, with a minimum of 4-V turn-off to a maximum 7.75-V turn-on. See the command descriptions for more details.

8.3.3 Turn-On and Turn-Off Delay and Sequencing

The TPS544x25 devices provide many sequencing options. Using the ON_OFF_CONFIG command, the device can be configured to start up whenever the input voltage is above the undervoltage lockout (UVLO) threshold, or to additionally require a signal on the CNTL pin and/or receive an update to the OPERATION command via the PMBus interface . When the gating signal as specified by ON_OFF_CONFIG is asserted, a programmable turn-on delay can be set with TON_DELAY to delay the start of regulation. Similarly, a programmable turn-off delay can be set with TOFF_DELAY to delay the stop of regulation once the gating signal is de-asserted. Delay times are specified in ms, from 0 to 100 ms.

Figure 32 shows control of the start-up and shutdown operations of the device, when the device is configured to respond to both CNTL and the OPERATION command. The device can also be configured to use either the CNTL signal, or the OPERATION command independently, or convert power whenever sufficient input voltage is present.

Figure 32. Turn-On Controlled By Both Operation⁽¹⁾ and Control ^{Bit 7 of OPERATION is used to control power conversion.}

1. Bit 7 of OPERATION is used to control power conversion.

8.3.4 Voltage Reference

A reference DAC (digital-to-analog converter) with 500 mV to 1500 mV range and 2^-9 V (1.953 mV) resolution connects to the non-inverting input of the error amplifier. The tight tolerance on the reference voltage allows the user to design power supply with very high DC accuracy.

8.3.5 Differential Remote Sense

The TPS544x25 devices implement a differential remote sense amplifier to provide excellent load regulation by cancelling IR-drop in high current applications. The VOUTS+ and VOUTS– pins should be kelvin-connected to the output capacitor bank directly at the load, and routed back to the device as a tightly coupled differential pair. Ensure that these traces are isolated from fast switching signals and high current paths on the final PCB layout, as these can add differential-mode noise. Optionally, use a small coupling capacitor (1-nF typical) between the VOUTS+ and VOUTS– pins to improve noise immunity. The output of the differential remote sense amplifier (DIFFO) is used for output voltage setting and error amplifier frequency compensation local to the device as shown in Figure 33.

Additionally, the voltage at the DIFFO pin is digitized, averaged to reduce measurement noise and continually stored in the READ_VOUT register, enabling output voltage telemetry.

Figure 33. Output Voltage Setting

8.3.6 Set Output Voltage and Adapative Voltage Scaling (AVS)

A voltage divider from the DIFFO pin to the FB pin is typically required to set the nominal output voltage like the one formed by R1 and R_BIAS resistors shown in Figure 33. To allow PMBus devices to map between the commanded voltage and the voltage at the control circuit input (V_OUT divided down to match a reference voltage), the device uses the VOUT_SCALE_LOOP command.

The output voltage can be set and adjusted dynamically using the VOUT_COMMAND through the PMBus interface. See the PMBus command description for full details on the implementation.

The range of valid VOUT_COMMAND values is dependent upon the configured VOUT_SCALE_LOOP as shows in Table 1.

There are several commands that are used in commanding the output voltage of a device with a PMBus interface. These include:

• VOUT_MODE
• VOUT_COMMAND
• VOUT_MAX
• MFR_VOUT_MIN
• VOUT_SCALE_LOOP
• VOUT_OV_FAULT_LIMIT
• VOUT_OV_WARN_LIMIT
• VOUT_UV_WARN_LIMIT
• VOUT_UV_FAULT_LIMIT

Figure 34 shows how the output voltage related commands are applied. The TPS544x25 devices implement relational check to make sure the VOUT_COMMAND is not programmed to exceed the VOUT_MAX, MFR_VOUT_MIN, VOUT_OV_WARN_LIMIT , and VOUT_UV_WARN_LIMIT. The VOUT_OV_WARN_LIMIT should also be smaller than VOUT_OV_FAULT_LIMIT and the VOUT_UV_WARN_LIMIT should be greater than VOUT_UV_FAULT_LIMIT. Violation of these relational check rules will set corresponding status bits and trigger SMBALERT. See the PMBus command description for full details.

In order for the relational checking to operate properly and to avoid error flagging, the VOUT_SCALE_LOOP should be changed first, if needed. Any changes to other registers should be made such that the values in all the registers conform to the limits for the current VOUT_SCALE_LOOP setting.

Figure 34. Conceptual View Of How Output Voltage Related Commands Are Applied

8.3.7 Reset VOUT

Without power cycling, the VOUT_COMMAND value and the corresponding output voltage can be reset to the default value set by VSET. To reset VOUT_COMMAND, the VSET pin should be used in combination with SYNC/RESET_B pin. The default VOUT_COMMAND value is set by the resistor connected between VSET and AGND and latched when the TPS544x25 devices are powered up from VDD. When the SYNC/RESET_B pin is pulled low, the digital core sets VOUT_COMMAND value back to the default value. The Figure 35 shows the timing diagram for resetting the output voltage. When RESET_B is asserted low, after a short delay (less than 2 µs), the output voltage begins transitioning from its current value to the default value configured by VSET per the slew-rate set in VOUT_TRANSITION_RATE. The VOUT_COMMAND value is not updated to any VOUT_COMMAND programming while SYNC/RESET_B is held low.

(A) VOUT_COMMAND adjustment through the PMBus interface ;

(B) Reset back to default VOUT_COMMAND value determined by VSET resistor at power up. The slew rate is defined by VOUT_TRANSITION_RATE.

Figure 35. Output Voltage Reset

8.3.8 Switching Frequency and Synchronization

A resistor from the RT pin to AGND sets the switching frequency. Equation 3 calculates the R_RT resistor value.

Equation 3.

where

• R_RT is the timing resistor in Ω
• f_SW is the switching frequency in Hz

The TPS544x25 devices are designed to operate between 200 kHz and 1 MHz.

The TPS544x25 devices can also synchronize to an external clock which is ±20% of the free-running frequency. The external clock should be applied to the SYNC/RESET_B pin. A sudden change in synchronization clock frequency causes an associated control loop response, resulting in an overshoot or undershoot on the output voltage.

If a resistor is connected from VSET pin to AGND to program the initial boot-up voltage, the clock synchronization function is disabled on default, the SYNC/RESET_B pin is configured to RESET function which can reset VOUT when SYNC/RESET_B is logic low.

In order to use both VSET and SYNC function, the FORCE_SYNC bit in register MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h) should be set to 1, as shown in Table 3. While the output in regulation and an external clock being applied to SYNC/RESET_B pin, set the FORCE_SYNC bit on the fly causes a sudden change in switching frequency and results in an overshoot or undershoot on the output voltage.

8.3.9 Soft-Start and TON_RISE Command

To control the inrush current needed to charge the output capacitor bank during start up, the TPS544x25 devices implement a soft-start time. When the device is enabled, the feedback reference voltage, V_REF, ramps from 0 V to the final level defined by VOUT_COMMAND and VOUT_SCALE_LOOP at a slew rate defined by the TON_RISE command. The rise times specified are defined by the slew rate needed to ramp the reference voltage from 0 V to its final value at each given rise time.

The actual rise time of the converter output is slightly less than the rise time defined by TON_RISE. This difference occurs because switching does not occur until the error amplifier output reaches the valley of the PWM ramp. During soft-start, the error amplifier output voltage starts at 0 V, and must reach the valley of the PWM ramp, 0.75 V typical, before switching can begin. As soons as it reaches the valley of the PWM ramp, the converter output voltage rises quickly until the feedback voltage, V_FB, reaches the reference voltage V_REF, from which point they track through the end of the soft-start period.

Figure 36. Soft-Start Timing

The TPS544x25 devices support several soft-start times between 1 ms and 100 ms selected by the TON_RISE command. The value of TON_RISE can be set through the PMBus interface or alternatively by the resistor connected from TSNS/SS pin to AGND. To use the TSNS/SS pin for TON_RISE setting, the SS_DET_DIS bit in OPTIONS (MFR_SPECIFIC_21) (E5h) register should be set to 0 to enable the soft-start time detection.

The E48 series resistors with no worse than 1% tolerance suggested for TON_RISE setting are shown in Table 5. Issuing TON_RISE command after start-up overwrites the TON_RISE value set by external resistor. If TPS544x25 re-starts after losing power completely, the TON_RISE value set by external resistor overwrites any value stored from previous TON_RISE operation.

8.3.10 Pre-Biased Output Start-Up

The TPS544x25 devices prevent current from being discharged from the output during start-up, when a pre-biased output condition exists. No SW pulses occur until the internal soft-start voltage rises above the error amplifier input voltage (FB pin), if the output is pre-biased. As soon as the soft-start voltage exceeds the error amplifier input, and SW pulses start, the device limits synchronous rectification after each SW pulse with a narrow on-time. The low-side MOSFET on-time slowly increases on a cycle-by-cycle basis until 128 pulses have been generated and the synchronous rectifier runs fully complementary to the high-side MOSFET. This approach prevents the sinking of current from a pre-biased output, and ensures the output voltage start-up and ramp-to-regulation sequences are smooth and monotonic. These devices respond to a pre-biased output over-voltage condition immediately upon VDD powered up and BP6 regulator voltage above its own UVLO of 3.73 V typical.

8.3.11 Soft-Stop and TOFF_FALL Command

As shown in Figure 32, the TPS544x25 devices implement TOFF_FALL command to define the time for the output voltage to drop from regulation to 0. There might be negative current in the TPS544x25 devices during the TOFF_FALL time in order to discharge the output voltage. The setting of TOFF_FALL of 0 ms means the unit to bring its output voltage down to 0 as quickly as possible, which results in an effective TOFF_FALL time of 1 ms (fastest time supported). This feature can be disabled in ON_OFF_CONFIG for the turn-off controlled by CNTL pin or bit 6 of OPERATION if the regulator is turned off by OPERATION command, in that case, both high-side and low-side FET drivers are turned off immediately and the output voltage will be discharged by the load.

8.3.12 Current Monitoring and Low-Side MOSFET Overcurrent Protection

The TPS544x25 devices sense average output current using an internal sense FET. A sense FET conducts a scaled-down version of the power-stage current. Sampling this current in the middle of the low-side drive signal determines the average output current. This architecture achieves excellent current monitoring and better overcurrent threshold accuracy than inductor DCR current sensing with minimal temperature variation and no dependence on power loss in a higher DCR inductor. Use the IOUT_CAL_OFFSET command to improve current sensing and overcurrent accuracy by removing board layout-related systematic errors post assembly. The devices continually digitize the sensed output current, and average it to reduce measurement noise. The devices then store the current value in the read-only READ_IOUT register, enabling output current telemetry.

Figure 37. SenseFET Average Current Sensing and Overcurrent Protection

The TPS544x25 devices also implement low-side MOSFET overcurrent protection with programmable fault and warning thresholds. The IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT commands set the low-side overcurrent thresholds.

As shown in Figure 37, if an overcurrent event is detected in a given switching cycle, the device increments an overcurrent counter. When the device detects three consecutive overcurrent (either high-side or low-side) events, the converter responds, flagging the appropriate status registers, triggering SMBALERT if it is not masked, and entering either continuous restart hiccup, or latch-off according to the IOUT_OC_FAULT_RESPONSE command. In continuous restart hiccup mode, the devices implement a seven soft-start cycle time-out, followed by a normal soft-start attempt. When the overcurrent fault clears, normal operation resumes, otherwise, the device detects overcurrent and the process repeats. The IOUT_OC_FAULT_RESPONSE can also be set to ignore the OC fault for debug purpose. The fault response scheme is summarized in Table 6.

8.3.13 High-Side MOSFET Short-Circuit Protection

The TPS544x25 devices also implement a fixed high-side MOSFET overcurrent (HSOC) protection to limit peak current, and prevent inductor saturation in the event of a short circuit. The devices detect an overcurrent event by sensing the voltage drop across the high-side MOSFET when it is on. If the peak current reaches the I_HOSC level on any given cycle, the cycle terminates to prevent the current from increasing any further. High-side MOSFET overcurrent events are counted using the method shown in Figure 37. If the devices detect three consecutive overcurrent events (high-side or low-side), the converter responds, by flagging the appropriate status registers; triggering SMBALERT if it is not masked; and entering either continuous restart hiccup, or latch-off according to the IOUT_OC_FAULT_RESPONSE command. For accurate high-side MOSFET overcurrent protection, the VIN and VDD pins must be the same potential; split rail operation is not supported. The IOUT_OC_FAULT_RESPONSE can also be set to ignore the OC fault for debug purpose. When the IOUT_OC_FAULT_RESPONSE is set to ignore, the device continues to have cycle-by-cycle HSOC protection. The fault response scheme is summarized in Table 6.

8.3.14 Over-Temperature Protection

An internal temperature sensor protects theTPS544x25 devices from thermal runaway. The internal thermal shutdown threshold, T_SD, is fixed at 145°C typical. When the devices sense a temperature above T_SD, an over-temperature fault internal (OTFI) bit in STATUS_MFR_SPECIFIC is flagged, and power conversion stops until the sensed junction temperature falls by the thermal shutdown hysteresis amount, T_HYST, (20°C typical). The SMBALERT will be triggered if it is not masked.

The TPS544x25 devices also provide programmable external over-temperature fault and warning thresholds using measurements from an external temperature sensor connected on the TSNS/SS pin as shown in Figure 38. The temperature sensor circuit applies two bias currents to an external NPN transistor, and measures ΔV_BE to infer the junction temperature of the sensor. The TPS544x25 devices are designed to use a standard 2N3904 NPN transistor as a temperature sensor. Other sensors may be used, but the devices assume an ideality factor, n, of 1.008 for use with the 2N3904 transistor. The devices then digitize the result and compare it to the user-configured over-temperature fault and warning thresholds. When an external over-temperature fault (OTF) is detected, power conversion stops until the sensed temperature falls by 20°C. The READ_TEMPERATURE_2 (8Eh) register is continually updated with the digitized temperature measurement, enabling temperature telemetry. The OT_FAULT_LIMIT (4Fh) and OT_WARN_LIMIT (51h) commands set over-temperature fault and warning thresholds via the PMBus interface. When an overtemperature event is detected, the device sets the appropriate flags in STATUS_TEMPERATURE (7Dh) and triggers SMBALERT if it is not masked.

TI recommends including a 1-nF capacitor between the TSNS/SS pin and AGND to reduce temperature measurement noise. Optionally, external temperature sensing can be disabled by terminating TSNS/SS to AGND with a 0-Ω resistor. This termination forces the external temperature measurement to –40°C, and prevents external over-temperature faults tripping. The internal temperature sensor, and internal over-temperature fault remain enabled regardless of the TSNS/SS pin termination.

The device response upon over-temperature fault can be set to Latch-off, Restart and Ignore in OT_FAULT_RESPONSE. The fault response scheme is summarized in Table 6.

Figure 38. Over-Temperature Protection

8.3.15 Output Overvoltage and Undervoltage Protection

The TPS544x25 devices include both output overvoltage protection and output undervoltage protection capability. The devices compare the DIFFO pin voltage to internal selectable pre-set voltages, as defined by the VOUT_OV_FAULT_LIMIT and VOUT_UV_FAULT_LIMIT command . As the output voltage rises or falls from the nominal voltage, the DIFFO voltage tracks the output voltage.

If the DIFFO pin voltage rises above the output overvoltage protection threshold VOUT_OV_FAULT_LIMIT, the device terminates normal switching and turns on the low-side MOSFET to discharge the output capacitor and prevent further increases in the output voltage. The device also declares an OV fault, flagging the appropriate status registers, triggering SMBALERT if it is not masked. Then the device enters continuous restart hiccup, or latch-off according to the VOUT_OV_FAULT_RESPONSE command. The TPS544x25 devices respond to the output over-voltage condition immediately upon VDD powered up and BP6 regulator voltage above its own UVLO of 3.73 V typical. The VOUT_OV_FAULT_RESPONSE can also be set to ignore the output overvotlage fault and continue without interruption. Under this configuration, the control loop continues to respond and adjust PWM duty cycle in order to keep output voltage within regulation.

If the DIFFO pin voltage falls below the undervoltage protection level defined by VOUT_UV_FAULT_LIMIT after soft-start has completed, the device terminates normal switching and forces both the high-side and low-side MOSFETs off, and awaits an external reset or begins a hiccup time-out delay prior to restart, depending on the value of the VOUT_UV_FAULT_RESPONSE command. The device also declares a UV fault, flagging the appropriate status registers, triggering SMBALERT if it is not masked. The VOUT_UV_FAULT_RESPONSE can also be set to ignore the output undervotlage fault and continue without interruption for debug purpose.

The fault response scheme is summarized in Table 6.

8.3.16 TON_MAX Fault

The TON_MAX_FAULT_LIMIT command sets an upper limit, in ms, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. The TPS544x25 devices differentiate a startup UV fault and a regulation UV fault by implementing the TON_MAX_FAULT_LIMIT . The TON_MAX_FAULT_LIMIT can allow the TPS544x25 devices more time than the soft-start time defined by TON_RISE to come into regulation and the UV detection is essentially delayed up to the TON_MAX_FAULT_LIMIT time. Refer to PMBus command section TON_MAX_FAULT_LIMIT for more details.

8.3.17 Power Good (PGOOD) Indicator

When the output voltage remains within the PGOOD window after the start-up period, PGOOD as an open-drain output is released, and rises to an externally supplied logic level. The PGOOD window is defined by VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT, which can be programmed through the PMBus interface, as shown in Figure 39. The PGOOD hystersis window scales with respect to VOUT_SCALE_LOOP, i.e. the OVW and UVW hystersis window of VOUT_SCALE_LOOP = 0.5 is twice the size of VOUT_SCALE_LOOP = 1 and just half of the size of VOUT_SCALE_LOOP = 0.25. The The PGOOD pin pulls low upon any fault condition on default. Please refer to Table 6 for the possible sources to pull down PGOOD pin.

The PGOOD signal can be connected to the CNTL pin of another device to provide additional controlled turn-on and turn-off sequencing.

(1) V_OUT is measured at the DIFFO pin.

Figure 39. PGOOD Threshold and Hysteresis

8.3.18 Fault Protection Responses

Table 6 Summarizes the various fault protections and associated responses.

8.3.19 Switching Node

The SW pin connects to the switching node of the power conversion stage and acts as the return path for the high-side gate driver. When configured as a synchronous buck stage, the voltage swing on SW normally traverses from below ground to well above the input voltage. Parasitic inductance in the high-side FET and the output capacitance (C_OSS) of both power FETs form a resonant circuit that can produce high frequency ( > 100 MHz) ringing on this node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the pin.

In many cases, a series resistor and capacitor snubber network connected from the switching node to GND can be helpful in damping the ringing and decreasing the peak amplitude. Provide provisions for snubber network components in the layout of the printed circuit board. If testing reveals that the ringing amplitude at the SW pin exceeds the limit, then include snubber components. See SLUP100 for more information about snubber circuits design.

Placing a BOOT resistor in series with the BOOT capacitor slows down the turn-on of the high-side FET and can help to reduce the peak ringing at the switching node as well.

8.3.20 PMBus General Description

Timing and electrical characteristics of the PMBus interface specification can be found in the PMB Power Management Protocol Specification, Part 1, revision 1.2 available at http://pmbus.org. The TPS544x25 devices support both the 100-kHz and 400-kHz bus timing requirements. The devices do not stretch pulses when communicating with the master device.

Communication over the PMBus interface can support the Packet Error Checking (PEC) scheme if desired. If the master supplies clock (CLK pin) pulses for the PEC byte, PEC is used. If the CLK pulses are not present before a STOP, the PEC is not used.

The devices support a subset of the commands in the PMBus 1.2 Power Management Protocol Specification. See Supported PMBus Commands for more information

The devices also support the SMBALERT response protocol. The SMBALERT response protocol is a mechanism by which a slave device (such as the TPS544x25 devices ) can alert the bus master that it is available for communication. The master processes this event and simultaneously accesses all slaves on the bus (that support the protocol) through the alert response address (ARA). Only the slave that caused the alert acknowledges this request. The host performs a modified receive byte operation to ascertain the slave address. At this point, the master can use the PMBus status commands to query the slave that caused the alert. By default these devices implement the auto alert response, a manufacturer specific improvement to the SMBALERT response protocol, intended to mitigate the issue of bus hogging. See Auto ARA Response for more information. For more information on the SMBus alert response protocol, see the System Management Bus (SMBus) specification.

The devices contain non-volatile memory that stores configuration settings and scale factors. However, the device does not save the settings programmed into this non-volatile memory. The STORE_DEFAULT_ALL (11h) command must be used to commit the current settings to non-volatile memory as device defaults. The settings that are capable of being stored in non-volatile memory are noted in their detailed descriptions.

8.3.21 PMBus Address

The PMBus specification requires that each device connected to the PMBus have a unique address on the bus. The TPS544x25 devices each have 64 possible addresses (0 through 63 in decimal) that can be assigned by connecting resistors from the ADDR0 and ADDR1 pins to AGND. The address is set in the form of two octal (0-7) digits, one digit for each pin. ADDR1 is the high order digit and ADDR0 is the low-order digit. These address selection resistors must be 1% tolerance or better. Using resistors other than the recommended values can result in devices responding to adjacent addresses.

The E48 series resistors with no worse than 1% tolerance suggested for each digit value are shown in Table 7.

The TPS544x25 devices also detect values that are out of range on the ADDR0 and ADDR1 pins. If the device detects that either pin has an out-of-range resistance connected to it, the device continues to respond to PMBus interface commands, but does so at address 127 decimal, which is outside of the possible programmed addresses. It is possible but not recommended to use the device in this condition, especially if other devices are present on the bus or if another device could possibly occupy the 127 decimal address.

Certain addresses in the I²C address space are reserved for special functions and it is possible to set the address of the devices to respond to these addresses. The user is responsible for knowing which of these reserved addresses are in use in a system and for setting the address of the devices accordingly so as not to interfere with other system operations. The devices can be set to respond to the global call address or 0. It is recommended not to set the devices to this address unless the user is certain that no other devices respond to this address and that the overall bus is not affected by having such an address present.

8.3.22 PMBus Connections

The TPS544x25 devices support both the 100-kHz and 400-kHz bus speeds, 1.8-V or 3.3-V and 5-V PMBus interface logic level. See the PMBus Interface section of the Electrical Characteristics and PMBus command OPTIONS (MFR_SPECIFIC_21) (E5h) for more information.

8.3.23 Auto ARA (Alert Response Address) Response

By default, the TPS544x25 devices implement the auto alert response, a manufacturer specific improvement to the standard SMBALERT response protocol defined in the SMBus specification. The auto alert response is designed to prevent SMBALERT monopolizing in the case of a persistent fault condition on the bus. The user can choose to disable the auto ARA response, and use the standard SMBALERT response as defined in the SMBus specification, by using bit EN_AUTO_ARA of the OPTIONS (MFR_SPECIFIC_21) (E5h) register.

In the case of a fault condition, the slave device experiencing the fault pulls down the shared SMBALERT line, to alert the host that a fault condition has occurred. To establish which slave device has experienced the fault, the host issues a modified receive byte operation to the alert response address (ARA), to which only the slave pulling down on SMBALERT should respond. The SMBus protocol provides a method for address arbitration in the case that multiple slaves on the same bus are experiencing fault conditions. Once the host has established the address of the offending device, it must take any necessary action to release the SMBALERT line. For more information on the standard SMBus alert response protocol, see the System Management Bus (SMBus) specification.

In the case of a non-persistent fault (a single-time event, such as an invalid command or data byte), the host can ascertain the address of the slave experiencing a fault using the standard ARA response, and simply issue CLEAR_FAULTS (03h) to release the SMBALERT line, and resume normal operation. However, in the case of a persistent fault (one which remains active for some time, such as a short-circuit, or thermal shutdown), once the device issues a CLEAR_FAULTS (03h) command, the fault immediately re-triggers, and SMBALERT continues to be pulled low. In this case, the device holds low the SMBALERT line until the host masks the SMBALERT line using SMBALERT_MASK and then issues the CLEAR_FAULTS (03h) command. Because the SMBALERT line remains low, the host cannot be alerted to other fault conditions on the bus until it clears SMBALERT. Figure 40 and Figure 41 illustrate this response.

Figure 40. Example Standard ARA Response to Non-Persistent Fault

Figure 41. Example Standard ARA Response to a Persistent Fault

In order to mitigate the problem of SMBALERT bus hogging described previously, the devices implement the Auto ARA response. When Auto ARA is enabled, the devices releases SMBALERT automatically after successfully responding to access from the host at the alert response address. In this case, even when the device is experiencing a persistent fault, it does not hold the SMBALERT line low following successful notification of the host, and the host can be alerted to other faults on the bus in the normal manner. Examples of the auto ARA response are illustrated in Figure 42 and Figure 43.

Figure 42. Example Auto ARA Response to Non-Persistent Fault

Figure 43. Example Auto ARA Response to Persistent Fault

8.4.1 Continuous Conduction Mode

The TPS544x25 devices operate in continuous conduction mode (CCM) at a fixed frequency, regardless of the output current. For the first 128 switching cycles, the low-side MOSFET on-time is slowly increased to prevent excessive current sinking in the event the device is started with a pre-biased output. Following the first 128 clock cycles, the low-side MOSFET and the high-side MOSFET on-times are fully complementary.

8.4.2 Operation with CNTL Signal Control

According to the value in the ON_OFF_CONFIG register, the TPS544x25 devices can be commanded to use the CNTL pin to enable or disable regulation, regardless of the state of the OPERATION command. The CNTL pin can be configured as either active high or active low (inverted) logic.

8.4.3 Operation with OPERATION Control

According to the value in the ON_OFF_CONFIG register, the TPS544x25 devices can be commanded to use the OPERATION command to enable or disable regulation, regardless of the state of the CNTL signal.

8.4.4 Operation with CNTL and OPERATION Control

According to the value in the ON_OFF_CONFIG register, the TPS544x25 devices can be commanded to require both a signal on the CNTL pin, and the OPERATION command to enable or disable regulation.

Table 8. Supported PMBus Commands and Default Values

8.6.1 OPERATION (01h)

The OPERATION command turns the device output on or off in conjunction with input from the CNTL signal. It is also used to set the output voltage to the upper or lower margin voltages. The unit stays in the commanded operating mode until a subsequent OPERATION command or a change in the state of the CNTL pin instructs the device to change to another mode.

8.6.2 ON_OFF_CONFIG (02h)

The ON_OFF_CONFIG command configures the combination of CNTL pin input and serial bus commands needed to turn the unit on and off. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL (11h) command. The default value in ON_OFF_CONFIG register is to have the device power up by CNTL pin only with the active high polarity and use the programmed turn-off delay (TOFF_DELAY) and ramp down (TOFF_FALL) for powering off the converter.

8.6.3 CLEAR_FAULTS (03h)

The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status registers simultaneously. At the same time, the device negates (clears, releases) its SMBALERT signal output if the device is asserting the SMBALERT signal. The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. If the fault is still present when the bit is cleared, the fault bit is immediately reset and the host notified by the usual means.

8.6.4 WRITE_PROTECT (10h)

The WRITE_PROTECT command is used to control writing to the PMBus device. The intent of this command is to provide protection against accidental changes. This command is not intended to provide protection against deliberate or malicious changes to the device configuration or operation. All supported command parameters may have their parameters read, regardless of the WRITE_PROTECT settings. Write protection also prevents protected registers from being updated in the event of a RESTORE_DEFAULT_ALL. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

8.6.5 STORE_DEFAULT_ALL (11h)

The STORE_DEFAULT_ALL command stores all of the current storable register settings in the EEPROM memory as the new defaults on power up.

It is permissible to use this command while the device is switching. Note however that the device continues to switch but ignores all fault conditions until the internal store process has completed. Issuing STORE_DEFAULT_ALL also causes the device to be unresponsive via PMBus for a period of ~100ms.

EEPROM programming faults cause the device to NACK and set the 'cml' bit in the STATUS_BYTE and the 'mem' bit in the STATUS_CML registers.

8.6.6 RESTORE_DEFAULT_ALL (12h)

The RESTORE_DEFAULT_ALL command restores all of the storable register settings from EEPROM memory to those registers which are unprotected according to current setting of WRITE_PROTECT. Issuing STORE_DEFAULT_ALL also causes the device to be unresponsive via PMBus for a period of ~100ms.

8.6.7 CAPABILITY (19h)

The CAPABILITY command provides a way for a host system to determine some key capabilities of this PMBus device.

The default values indicate that the device supports Packet Error Checking (PEC), a maximum bus speed of 400 kHz (SPD) and the SMBus Alert Response Protocol using SMBALERT.

8.6.8 SMBALERT_MASK (1Bh)

The SMBALERT_MASK command may be used to prevent a warning or fault condition from asserting the SMBALERT signal.

The bits in the mask byte align with the bits in the corresponding status register. For example, if the STATUS_TEMPERATURE command were sent with the mask byte 01000000b, then an Over Temperature Warning condition would be blocked from asserting SMBALERT. Please refer to the PMBus v1.2 specification - section 15.38 (SMBALERT_MASK Command) and the SMBus specification Block Write/Block Read protocol for further details.

There are 19 maskable SMBALERT sources in the TPS544x25. Each of these 19 status conditions has an associated EEPROM backed mask bit. These sources are represnted and identified in the status register command descriptions by a particular status bit denoted as having EEPROM backup (e.g. a bit access of r/w^E). Writes and reads to SMBALERT_MASK command code accepts only the following as valid STATUS_x command codes:

• STATUS_WORD
• STATUS_VOUT
• STATUS_IOUT
• STATUS_INPUT
• STATUS_TEMPERATURE
• STATUS_CML
• STATUS_MFR_SPECIFIC

Attempting to write a mask byte for any STATUS_X command code other than this list causes the device to set the ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers, and triggers SMBALERT. Attempting to read a mask byte for any STATUS_x command code other than this list returns 00h for the mask byte. Refer to these individual command descriptions for further details on their specific smbalert masking capabilities.

There is 1 unique status bit in the TPS544x25 that warrants special clarification: PGOOD_Z (STATUS_WORD[10]) is maskable as an SMBALERT source via SMBALERT_MASK commands to STATUS_WORD. If the user wants to write, or read, the mask bit for PGOOD_Z, they must put ‘79h’ in the STATUS_x COMMAND_CODE field of the SMBALERT_MASK command. PGOOD_Z SMBALERT_MASK bit default to 1.

8.6.9 VOUT_MODE (20h)

The PMBus specification dictates that the data word for the VOUT_MODE command is one byte that consists of a 3-bit mode and 5-bit exponent parameter, as shown below. The 3-bit mode sets whether the device uses the Linear or Direct modes for output voltage related commands. The 5-bit parameter sets the exponent value for the linear data mode. The mode and exponent parameters are fixed and do not permit the user to change the values.

8.6.10 VOUT_COMMAND (21h)

The VOUT_COMMAND command sets the output voltage in volts. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command. The exponent is set be VOUT_MODE at –9 (equivalent of 1.953 mV/count). The programmed the output voltage is computed as:

The range of valid VOUT_COMMAND values is dependent upon the configured VOUT_SCALE_LOOP (29h) as follows:

There are 2 “invalid data” situations that are possible and checked in hardware. They are handled differently:

• The first case is if the value programmed to VOUT_COMMAND exceeds the value stored in either MFR_VOUT_MIN (A4h) or VOUT_MAX (24h). In this case, VOUT_COMMAND is set to the appropriate MFR_VOUT_MIN or VOUT_MAX value (which ever was violated). See the command descriptions for MFR_VOUT_MIN (A4h) or VOUT_MAX (24h) for the specific status bits set in either case.
• The second case is if VOUT_COMMAND is attempted to be programmed outside the OV and UV warn limits. In this case, the VOUT_COMMAND value remains unchanged. Specifically, the following relationships must be maintained:

• VOUT_COMMAND < VOUT_OV_WARN_LIMIT
• VOUT_COMMAND > VOUT_UV_WARN_LIMIT

In this second case where VOUT_COMMAND is attempted to be programmed outside the OV or UV Warn limits, it causes the device to set the ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers, and triggers SMBALERT signal.

When using the VSET function, at initial power-up. the Mantissa value decoded according to the appropriate VSET resistor is written into the VOUT_COMMAND register as the initial default. Note this overwrites any value restored from EEPROM when the device VDD is powered up.

8.6.11 VOUT_MAX (24h)

The VOUT_MAX command sets the maximum output voltage. The purpose is to protect the device(s) on the output rail supplied by this device from a higher than acceptable output voltage. VOUT_MAX imposes an upper bound to any attempted output voltage setting:

a) programmed VOUT_COMMAND

b) VSET pin default

If any attempt is made to program the output voltage (using the VOUT_COMMAND ) in excess of the value in VOUT_MAX, the device also:

• Clamps the output voltage at the programmed VOUT_MAX value
• Sets the OTH (other) bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the VOUT_MAX_Warning bit in the STATUS_VOUTregister
• Notifies the host via the SMBALERT pin

The exponent is set be VOUT_MODE at –9 (equivalent of 1.953 mV/count). The programmed output voltage is computed as:

There are 2 “invalid data” situations that are possible and checked in hardware. They are handled differently:

• If the commanded VOUT_MAX is outside the valid data range for the VOUT_SCALE_LOOP configured, but, is still relationally correct (above VOUT_COMMAND). In this case, that value is not accepted; but, VOUT_MAX is set to the highest allowed value.
• The second case is the opposite, where the attempted write value is within the absolute range of VOUT_MAX; but, is not relationally correct (it is below VOUT_COMMAND). In this case, VOUT_MAX remains unchanged.

Both cases equally cause the device to set the ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers, and triggers SMBALERT signal.

8.6.12 VOUT_TRANSITION_RATE (27h)

The VOUT_TRANSITION_RATE command sets the rate of change in mV/µs of any output voltage change during normal operation (also includes vout changes in TOFF_DELAY state. In contrast Soft Start transition rate is controlled by TON_RISE and the TOFF_FALL transition rate is controlled by TOFF_FALL command).

Only 8 fixed output voltage transition rates are available in the device. As such, the range of programmed vout_transition rates are sub-divided into 8 “buckets” that then selects one of the 8 fixed V_OUT transition rates. Programmed values are rounded to the nearest “bucket/transition rate” as outlined in the table below.

8.6.13 VOUT_SCALE_LOOP (29h)

VOUT_SCALE_LOOP is equal to the feedback resistor ratio ( R_BIAS /( R_BIAS +R1) in the configuration shown in Figure 33). It is limited to only 3 possible options/ratios: 1 (default, no R_BIAS needed), 0.5, and 0.25. Attempting to write a value unequal to one of these three options cause the device to set the ’cml’ bit in the STATUS_BYTE, and the ‘ivd’ bit in the STATUS_CML registers. Additionally, SMBALERT is asserted and the value of VOUT_SCALE_LOOP remains unchanged. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

In order for the range checking to work properly and to avoid Invalid Data scenarios:

• VOUT_SCALE_LOOP should be changed first, if needed.
• Any changes to these registers should be made such that:
  • The values in all the registers conform to the limits for the current VOUT_SCALE_LOOP setting
  • The order below is optimum for programming the output voltage upwards (not all commands may be necessary)
    • (40h) VOUT_OV_FAULT_LIMIT
    • (42h) VOUT_OV_WARN_LIMIT
    • (24h) VOUT_MAX (ordering with respect to VOUT_OV_FAULT_LIMIT and VOUT_OV_WARN_LIMIT is irrelevant. Just set VOUT_MAX prior to VOUT_COMMAND)
    • (21h) VOUT_COMMAND
    • (A4h) MFR_VOUT_MIN (ordering with respect to VOUT_UV_FAULT_LIMIT and VOUT_UV_WARN_LIMIT is irrelevant. Just set MFR_VOUT_MIN after VOUT_COMMAND)
    • (43h) VOUT_UV_WARN_LIMIT
    • (44h) VOUT_UV_FAULT_LIMIT
  • The order below is optimum for programming the output voltage downwards (not all commands may be necessary)
    • (44h) VOUT_UV_FAULT_LIMIT
    • (43h) VOUT_UV_WARN_LIMIT
    • (A4h) MFR_VOUT_MIN (ordering with respect to VOUT_UV_FAULT_LIMIT and VOUT_UV_WARN_LIMIT is irrelevant. Simply set MFR_VOUT_MIN prior to VOUT_COMMAND)
    • (21h) VOUT_COMMAND
    • (24h) VOUT_MAX (ordering with respect to VOUT_OV_FAULT_LIMIT and VOUT_OV_WARN_LIMIT is irrelevant. Simply set VOUT_MAX after VOUT_COMMAND)
    • (42h) VOUT_OV_WARN_LIMIT
    • (40h) VOUT_OV_FAULT_LIMIT

8.6.14 VIN_ON (35h)

The VIN_ON command sets the value of the input voltage at which the unit should start operation assuming all other required startup conditions are met. Values are mapped to the nearest supported increment. Values outside the supported range are treated as invalid data and cause the device set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers, and trigger SMBALERT signal. The value of VIN_ON remains unchanged on an out-of-range write attempt. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

The supported VIN_ON values are shown in Table 9:

VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF higher than VIN_ON results in the new value being rejected, SMBALERT signal being asserted along with the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

The data word that accompanies this command is divided into a fixed 5-bit exponent and an 11-bit mantissa. The four most significant bits of the mantissa are fixed, while the lower 4 bits may be altered.

8.6.15 VIN_OFF (36h)

The VIN_OFF command sets the value of the input voltage at which the unit should stop operation. Values are mapped to the nearest supported increment. Values outside the supported range is treated as invalid data and causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers, and trigger SMBALERT signal. The value of VIN_OFF remains unchanged during an out-of-range write attempt. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

The supported VIN_OFF values are shown in Table 10:

VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF higher than VIN_ON results in the new value being rejected, SMBALERT being asserted along with the cml bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

The data word that accompanies this command is divided into a fixed 5 bit exponent and an 11 bit mantissa. The 4 most significant bits of the mantissa are fixed, while the lower 7 bits may be altered.

8.6.16 IOUT_CAL_OFFSET (39h)

The IOUT_CAL_OFFSET is used to compensate for offset errors in the READ_IOUT results and the IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT thresholds. The units are amperes. The default setting is 0 A. The resolution of the argument for this command is 62.5 mA and the range is +3.9375 A to -4.0 A. Values written outside of this range alias into the supported range. This occurs because the read-only bits are fixed. The exponent is always –4 and the 5 msb bits of the Mantissa are always equal to the sign bit. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

8.6.17 VOUT_OV_FAULT_LIMIT (40h)

The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage that causes an output overvoltage fault. Attempts to write values outside of the acceptable range is treated as invalid data, causing the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal. Additionally, the value of VOUT_OV_FAULT_LIMIT remains unchanged. Maintaining values within “acceptable range” also means:

VOUT_OV_WARN_LIMIT < VOUT_OV_FAULT_LIMIT < (922d/VOUT_SCALE_LOOP)

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command. Note the lower 4 bits can not be backed up in EEPROM.

The VOUT_OV_FAULT_LIMIT takes a two-byte data word formatted as shown below:

8.6.18 VOUT_OV_FAULT_RESPONSE (41h)

The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to a VOUT_OV_FAULT_LIMIT fault. The device also:

• Sets the OVF bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the OVF bit in the STATUS_VOUT register, and
• Notifies the host by asserting SMBALERT

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to a output overvoltage fault.

The default response to a output overvoltage fault is to shut down and restart with 7 × TON_RISE time delay.

8.6.19 VOUT_OV_WARN_LIMIT (42h)

The VOUT_OV_WARN_LIMIT command sets the value of the output voltage that causes an output overvoltage warning condtion. Attempts to write values outside of the acceptable range is treated as invalid data, causing the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal. Additionally, the value of VOUT_OV_WARN_LIMIT remains unchanged. Maintaining values within “acceptable range” also means:

• VOUT_COMMAND < VOUT_OV_WARN_LIMIT < VOUT_OV_FAULT_LIMIT
• 269d < VOUT_OV_WARN_LIMIT × VOUT_SCALE_LOOP

The device also:

• Sets the oth bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the OVW bit in the STATUS_VOUT register, and
• Notifies the host by asserting SMBALERT

The VOUT_OV_WARN_LIMIT takes a two-byte data word formatted as shown below:

8.6.20 VOUT_UV_WARN_LIMIT (43h)

The VOUT_UV_WARN_LIMIT command sets the value of the output voltage that causes an output undervoltage warning condtion. This warning is masked until the unit reaches the programmed output voltage. This warning is also masked when the unit is disabled. Attempts to write values outside of the acceptable range is treated as invalid data, causing the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal. Additionally, the value of VOUT_UV_WARN_LIMIT remains unchanged. Maintaining values within “acceptable range” also means:

• VOUT_UV_FAULT_LIMIT < VOUT_UV_WARN_LIMIT < VOUT_COMMAND
• 178d < VOUT_UV_WARN_LIMIT × VOUT_SCALE_LOOP < 732d

The device also:

• Sets the oth bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the UVW bit in the STATUS_VOUT register, and
• Notifies the host by asserting SMBALERT

The VOUT_UV_WARN_LIMIT takes a two-byte data word formatted as shown below:

8.6.21 VOUT_UV_FAULT_LIMIT (44h)

The VOUT_UV_FAULT_LIMIT command sets the value of the output voltage that causes an output undervoltage fault. This fault is masked until the unit reaches the programmed output voltage. This fault is also masked when the unit is disabled. Attempts to write values outside of the acceptable range is treated as invalid data, causing the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal. Additionally, the value of VOUT_UV_FAULT_LIMIT remains unchanged. Maintaining values within “acceptable range” also means:

• 176d/VOUT_SCALE_LOOP < VOUT_UV_FAULT_LIMIT < VOUT_UV_WARN_LIMIT

A VOUT_UV_FAULT_LIMIT of 0000h shall be a means of disabling VOUT_UV_FAULT response and reporting completely and is the only exception to the above “acceptable range” requirements. Disabling means that the unit does not check for Vout_UVF faults; thus there is no setting of UVF status bits, nor associated SMBALERT triggering. Disabling VOUT_UV_FAULT_LIMIT (by setting it to 0000h) has no bearing on VOUT_UV_WARN_LIMIT checking – which is considered a completely separate function.

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command. Note the lower 4 bits can not be backed up in EEPROM.

The VOUT_UV_FAULT_LIMIT takes a two-byte data word formatted as shown below:

8.6.22 VOUT_UV_FAULT_RESPONSE (45h)

The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to a VOUT_UV_FAULT_LIMIT fault. The device also:

• Sets the oth bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the UVF bit in the STATUS_VOUT register, and
• Notifies the host by asserting SMBALERT

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to a output undervoltage fault.

The default response to a output undervoltage fault is to shut down and restart with 7 × TON_RISE time delay.

8.6.23 IOUT_OC_FAULT_LIMIT (46h)

The IOUT_OC_FAULT_LIMIT command sets the value of the output current, in amperes, that causes the overcurrent detector to indicate an overcurrent fault condition. The IOUT_OC_FAULT_LIMIT should be set equal to or greater than the IOUT_OC_WARN_LIMIT. Writing a value to IOUT_OC_FAULT_LIMIT less than IOUT_OC_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

The IOUT_OC_FAULT_LIMIT takes a two-byte data word formatted as shown below:

8.6.23.2 Mantissa

The upper four bits are fixed at 0.

The lower seven bits are programmable.

The actual output current for a given mantissa and exponent is shown in Equation 6.

Equation 6.

The default values and allowable ranges for each device are summarized below:

DEVICE	OC_FAULT_LIMIT			UNIT
	MIN	DEFAULT	MAX
TPS544C25	5	36	40	A
TPS544B25	5	24	36	A

8.6.24 IOUT_OC_FAULT_RESPONSE (47h)

The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an IOUT_OC_FAULT_LIMIT or a VOUT undervoltage (UV) fault. The device also:

• Sets the OCF bit in the STATUS_BYTE
• Sets the OCFW bit in the STATUS_WORD
• Sets the OCF bit in the STATUS_IOUT register, and
• Notifies the host by asserting SMBALERT

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to an over current fault.

The default response to an over current fault is to shut down and restart with 7 × TON_RISE time delay.

8.6.25 IOUT_OC_WARN_LIMIT (4Ah)

The IOUT_OC_WARN_LIMIT command sets the value of the output current, in amperes, that causes the over-current detector to indicate an over-current warning. When this current level is exceeded the device:

• Sets the oth bit in the STATUS_BYTE
• Sets the OCFW bit in the STATUS_WORD
• Sets the OCW bit in the STATUS_IOUT register, and
• Notifies the host by asserting SMBALERT

The IOUT_OC_WARN_LIMIT threshold should always be set to less than or equal to the IOUT_OC_FAULT_LIMIT. Writing a value to IOUT_OC_WARN_LIMIT greater than IOUT_OC_FAULT_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal.

The default IOUT_OC_WARN_LIMIT is always set to fixed, relative IOUT_OC_FAULT_LIMIT - 2 A. Since the IOUT_OC_WARN_LIMIT is not stored in EEPROM, the IOUT_OC_WARN_LIMIT register is set to 2 A less than the stored IOUT_OC_FAULT_LIMIT upon any RESTORE from EEPROM.

The IOUT_OC_WARN_LIMIT takes a two byte data word formatted as shown below:

8.6.25.2 Mantissa

The upper four bits are fixed at 0.

Lower seven bits are programmable.

The actual output warning current level for a given mantissa and exponent is:

Equation 7.

The default values and allowable ranges for each device are summarized below:

DEVICE	OC_WARN_LIMIT			UNIT
	MIN	DEFAULT	MAX
TPS544C25	4	34	39.5	A
TPS544B25	4	22	35.5

8.6.26 OT_FAULT_LIMIT (4Fh)

The OT_FAULT_LIMIT command sets the value of the temperature, in degrees Celsius, that causes an over-temperature fault condition, when the sensed temperature from the external sensor exceeds this limit.

The OT_FAULT_LIMIT must always be greater than the OT_WARN_LIMIT. Writing a value to OT_FAULT_LIMIT less than or equal to OT_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as asserts the SMBALERT signal. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

The OT_FAULT_LIMIT takes a two byte data word formatted as shown below.

8.6.27 OT_FAULT_RESPONSE (50h)

The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an OT_FAULT_LIMIT. The device also:

• Sets the OTFW bit in the STATUS_BYTE
• Sets the OTF bit in the STATUS_TEMPERATURE
• Notifies the host by asserting SMBALERT

Once the over-temperature fault is tripped, the fault flag is latched until the external sensed temperature falls 20°C from the OT_FAULT_LIMIT.

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to an over temperature fault.

The default response to an over current fault is to shut down and restart with 7 × TON_RISE time delay.

8.6.28 OT_WARN_LIMIT (51h)

The OT_ WARN _LIMIT command sets the value of the temperature, in degrees Celsius, that causes an over-temperature warning condition, when the sensed temperature from the external sensor exceeds this limit. Upon triggering the over-temperature warning, the device takes the following actions:

• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the OT Warning bit in the STATUS_TEMPERATURE
• Notifies the host by asserting SMBALERT

Once the over-temperature warning is tripped, the warning flag is latched until the external sensed temperature falls 20°C from the OT_WARN_LIMIT.

The OT_WARN_LIMIT must always be less than the OT_FAULT_LIMIT. Writing a value to OT_WARN_LIMIT greater than or equal to OT_FAULT_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal.

The default OT_WARN_LIMIT is mathematically derived from the EEPROM backed OTF limit by subtracting 25 from (4Fh) OT_FAULT_LIMIT to reach the default OT_WARN_LIMIT. If the calculated OTW is less than 100 °C, then the default value is set to 100 °C. OTW=max(OTF-25, 100)

The OT_WARN_LIMIT takes a two byte data word formatted as shown below:

8.6.29 TON_DELAY (60h)

The TON_DELAY command sets the time in milliseconds, from when a start condition is received to when the output voltage starts to rise. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

The TON_DELAY command is formatted as a linear mode two’s complement binary integer.

Only 16 fixed TON_DELAY times are available in the device. As such, the range of programmed TON_DELAY settings are sub-divided into 16 “buckets” that then selects one of the 16 supported times. Programmed values are rounded to the nearest “bucket/transition rate” as outlined in the table Supported TON_DELAY Values:

8.6.30 TON_RISE (61h)

The TON_RISE command sets the time in milliseconds, from when the reference starts to rise until the voltage has entered the regulation band. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Programming a value of 0 instructs the unit to bring its output voltage to the programmed regulation value as quickly as possible. For TPS544x25, this results in an effective TON_RISE time of 1ms (fastest time supported).

If the Soft-Start Detection feature is being used (bit in MFR_??), then the Mantissa value decoded or derived by from the appropriate SS resistor writes into the TON_RISE register as the initial default. Note: This write overwrites any value restored from the EEPROM restore operation at initial power-up.

TON_RISE should always be set less than the TON_MAX_FAULT_LIMIT. Attempting to write a value to TON_RISE greater than TON_MAX_FAULT_LIMIT is not accepted and causes the device to set the ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers and asserts the SMBALERT signal.

There is one exception to this rule: when TON_MAX_FAULT_LIMIT is set to 0. This indicates that the TON_MAX_FAULT timer is disabled, which means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. If TON_MAX_FAULT_LIMIT = 0 (disabled), the relational cross check against TON_MAX_FAULT_LIMIT is also disabled.

The TON_RISE command is formatted as a linear mode two’s complement binary integer.

The supported TON_RISE times over PMBus are shown in Table 12:

8.6.31 TON_MAX_FAULT_LIMIT (62h)

The TON_MAX_FAULT_LIMIT command sets an UPPER limt in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. The time begins counting as soon as the device enters the soft-start state begins to ramp the output. In other words, the TON_MAX_FAULT_LIMIT timer starts at the beginning of the TON_RISE state.

The TON_MAX_FAULT_LIMIT should always be set greater than the TON_RISE. Attempting to write a value to TON_MAX_FAULT_LIMIT less than TON_RISE is not accepted and causes the device to set the ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers and asserts the SMBALERT signal.

There is one exception to this rule: when TON_MAX_FAULT_LIMIT is set to 0. This setting indicates that the TON_MAX_FAULT timer is disabled, which means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. If TON_MAX_FAULT_LIMIT = 0 (disabled), the relational cross check against TON_MAX_FAULT_LIMIT is also disabled.

The TON_MAX_FAULT_LIMIT command is formatted as a linear mode two’s complement binary integer.

The supported TON_MAX_FAULT_LIMIT times over PMBus are shown in Supported TON_MAX_FAULT_LIMIT Values:

8.6.32 TON_MAX_FAULT_RESPONSE (63h)

The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to an TON_MAX_FAULT_LIMIT.

The device also:

• Sets the oth bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the TONMAXF bit in the STATUS_VOUT register, and
• Notifies the host by asserting SMBALERT

The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to a TON_MAX_FAULT.

The default response to a TON_MAX_FAULT is to shut down and restart with 7 × TON_RISE time delay.

8.6.33 TOFF_DELAY (64h)

The TOFF_DELAY command sets the time in milliseconds, from when a stop condition is received and when the output voltage starts to fall. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

The TOFF_DELAY command is formatted as a linear mode two’s complement binary integer.

Only 16 fixed TOFF_DELAY times are available in the device. As such, the range of programmed TOFF_DELAY settings are sub-divided into 16 “buckets” that then selects one of the 16 supported times. Programmed values are rounded to the nearest “bucket/transition rate” as outlined in the table Supported TOFF_DELAY Values:

8.6.34 TOFF_FALL (65h)

The TOFF_FALL command sets the time in ms, from the end of the TOFF_DELAY time until the voltage reaches 0 V. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.

Programming a value of 0 instructs the unit to bring its output voltage down to 0 as quickly as possible. For TPS544x25, this results in actively ramping down the output voltage in 1 ms (the fastest supported ramp down).

The TOFF_FALL command is formatted as a linear mode two’s complement binary integer.

The supported TOFF_FALL times over PMBus are shown in Supported TOFF_FALL Values:

8.6.35 STATUS_BYTE (78h)

The STATUS_BYTE command returns one byte of information with a summary of the most critical device faults.

A "1" in any of these bit positions indicates that:

8.6.36 STATUS_WORD (79h)

The STATUS_WORD command returns two bytes of information with a summary of the device fault and warning conditions. The low byte is identical to the STATUS_BYTE above. The additional byte reports the warning conditions for output overvoltage and overcurrent, as well as the power good status of the converter.

A "1" in any of the high byte bit positions indicates that:

8.6.37 STATUS_VOUT (7Ah)

The STATUS_VOUT command returns one byte of information relating to the status of the output voltage related faults.

A "1" in any of these bit positions indicates that:

8.6.38 STATUS_IOUT (7Bh)

The STATUS_IOUT command returns one byte of information relating to the status of the output current related faults.

A "1" in any of these bit positions indicates that:

8.6.39 STATUS_INPUT (7Ch)

The STATUS_INPUT command returns one byte of information relating to the status of the converter's input related faults.

A "1" in any of these bit positions indicates that:

8.6.40 STATUS_TEMPERATURE (7Dh)

The STATUS_TEMPERATURE command returns one byte of information relating to the status of the external temperature related faults.

A "1" in any of these bit positions indicates that:

8.6.41 STATUS_CML (7Eh)

The STATUS_CML command returns one byte of information relating to the status of the converter’s communication related faults.

A "1" in any of these bit positions indicates that:

8.6.42 STATUS_MFR_SPECIFIC (80h)

The STATUS_MFR_SPECIFIC command returns one byte of information relating to the status of manufacturer-specific faults or warnings.

A "1" in any of these bit positions indicates that:

8.6.43 READ_VOUT (8Bh)

The READ_VOUT commands returns two bytes of data in the linear data format that represent the output voltage of the controller. The output voltage is sensed at the remote sense amplifier output pin so voltage drop to the load is not accounted for. The data format is as shown below:

8.6.43.2 Mantissa

The output voltage calculation is shown below.

Equation 8.

8.6.44 READ_IOUT (8Ch)

The READ_IOUT commands returns two bytes of data in the linear data format that represent the output current of the converter. The average output current is sensed according to the method described in Low-Side MOSFET Current Sensing and Overcurrent Protection. The data format is as shown below:

The device scales the output current before it reaches the internal analog to digital converter so that resolution of the output current read is 62.5 mA. The maximum value that can be reported is 40 A. The user must set the IOUT_CAL_OFFSET parameter correctly in order to obtain accurate results. Calculate the output current using Equation 9.

Equation 9.